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| this is information on a product in full production. july 2016 docid024244 rev 10 1/240 stm32f437xx stm32f439xx arm cortex-m4 32b mcu+fpu, 225dmips, up to 2mb flas h/256+4kb ram, crypto, usb otg hs/fs, ethernet, 17 tims, 3 adcs , 20 comm. interfaces, camera&lcd-tft datasheet - production data features ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 180 mhz, mpu, 225 dmips/1.25 dmips/mhz (dhrystone 2.1), and dsp instructions ? memories ? up to 2 mb of flash memory organized into two banks allowing read-while-write ? up to 256+4 kb of sram including 64-kb of ccm (core coupled memory) data ram ? flexible external memory controller with up to 32-bit data bus: sram,psram,sdram/lpsdr sdram , compact flash/nor/nand memories ? lcd parallel interface, 8080/6800 modes ? lcd-tft controller up to xga resolution with dedicated chrom-art accelerator? for enhanced graphic content creation (dma2d) ? clock, reset and supply management ? 1.7 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? low power ? sleep, stop and standby modes ?v bat supply for rtc, 2032 bit backup registers + optional 4 kb backup sram ? 312-bit, 2.4 msps adc: up to 24 channels and 7.2 msps in triple interleaved mode ? 212-bit d/a converters ? general-purpose dma: 16-stream dma controller with fifos and burst support ? up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 180 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? debug mode ? swd & jtag interfaces ? cortex-m4 trace macrocell? ? up to 168 i/o ports wit h interrupt capability ? up to 164 fast i/os up to 90 mhz ? up to 166 5 v-tolerant i/os ? up to 21 communica tion interfaces ? up to 3 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts/4 uarts (11.25 mbit/s, iso7816 interface, lin, irda, modem control) ? up to 6 spis (45 mbits/s), 2 with muxed full-duplex i 2 s for audio class accuracy via internal audio pll or external clock ? 1 x sai (serial audio interface) ? 2 can (2.0b active ) and sdio interface ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii ? 8- to 14-bit parallel camera interface up to 54 mbytes/s ? cryptographic acceleration: hardware acceleration for aes 128, 192, 256, triple des, hash (md5, sha- 1, sha-2), and hmac ? true random number generator ? crc calculation unit ? rtc: subsecond accuracy, hardware calendar ? 96-bit unique id lqfp100 (14 14 mm) lqfp144 (20 20 mm) ufbga176 (10 x 10 mm) lqfp176 (24 24 mm) lqfp208 (28 x 28 mm) wlcsp143 tfbga216 (13 x 13 mm) ufbga169 (7 7 mm) & " ' ! www.st.com
stm32f437xx and stm32f439xx 2/240 docid024244 rev 10 table 1. device summary reference part number stm32f437xx stm32f437vg, stm32f437zg, stm32f437ig, stm32f437vi, stm32f437zi, STM32F437II, stm32f437ai stm32f439xx stm32f439vi, stm32f439vg, stm32f439zg, stm32f439zi, stm32f439ig, stm32f439ii, stm32f439bg, stm32f439bi, stm32f439ni, stm32f439ai, stm32f439ng docid024244 rev 10 3/240 stm32f437xx and stm32f439xx contents 6 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 arm ? cortex?-m4 with fpu and embedded flash and sram . . . . . . . 20 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 20 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 21 3.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 flexible memory controller (fmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10 lcd-tft controller (available only on stm32f439xx) . . . . . . . . . . . . . . 23 3.11 chrom-art accelerator? (dma2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.15 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.16 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18.3 regulator on/off and inte rnal reset on/off availability . . . . . . . . . . 31 3.19 real-time clock (rtc), backup sram and backup registers . . . . . . . . . . 31 3.20 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.21 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 contents stm32f437xx and stm32f439xx 4/240 docid024244 rev 10 3.22 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.22.1 advanced-control timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.22.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.22.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.22.4 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.5 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.23 inter-integrated circuit interface ( i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.24 universal synchronous/asynchronous re ceiver transmitters (usart) . . 36 3.25 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.26 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.27 serial audio interface (sai1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.28 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.29 audio and lcd pll(pllsai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.30 secure digital input/output interface (sdio) . . . . . . . . . . . . . . . . . . . . . . . 39 3.31 ethernet mac interface with dedicated dma and ieee 1588 support . . . 39 3.32 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.33 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 40 3.34 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . . . 40 3.35 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.36 cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.37 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.38 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.39 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.40 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.41 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.42 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.43 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 docid024244 rev 10 5/240 stm32f437xx and stm32f439xx contents 6 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.2 vcap1/vcap2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 97 6.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 97 6.3.5 reset and power control block characterist ics . . . . . . . . . . . . . . . . . . . 98 6.3.6 over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.8 wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.9 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.10 internal clock source char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.11 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.12 pll spread spectrum clock generatio n (sscg) characteristics . . . . . 127 6.3.13 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.14 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.15 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 133 6.3.16 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.17 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.3.18 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.19 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.20 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.21 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.24 reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 6.3.25 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.3.26 fmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.27 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 194 6.3.28 lcd-tft controller (ltdc) characteristics . . . . . . . . . . . . . . . . . . . . . 195 contents stm32f437xx and stm32f439xx 6/240 docid024244 rev 10 6.3.29 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 197 6.3.30 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.1 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 7.2 wlcsp143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.3 lqfp144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 7.4 lqfp176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 7.5 lqfp208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 7.6 ufbga169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 7.7 ufbga176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 7.8 tfbga216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 7.9 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 appendix a recommendations when using inte rnal reset off . . . . . . . . . . . 228 a.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 appendix b application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 b.1 usb otg full speed (fs) interface solutions . . . . . . . . . . . . . . . . . . . . . 229 b.2 usb otg high speed (hs) interface solutions . . . . . . . . . . . . . . . . . . . . 231 b.3 ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 docid024244 rev 10 7/240 stm32f437xx and stm32f439xx list of tables 9 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. stm32f437xx and stm32f439xx features and peri pheral counts . . . . . . . . . . . . . . . . . . 15 table 3. voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 28 table 4. regulator on/off and internal reset on/off availability. . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5. voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 10. stm32f437xx and stm32f439xx pin and ball definiti ons . . . . . . . . . . . . . . . . . . . . . . . . 52 table 11. fmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 12. stm32f437xx and stm32f439xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 74 table 13. stm32f437xx and stm32f439xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 86 table 14. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 15. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 16. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 17. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 18. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 96 table 19. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 20. operating conditions at power-up / power-down (r egulator on) . . . . . . . . . . . . . . . . . . . . 97 table 21. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . . 97 table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 23. over-drive switching characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 24. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram . . . . . . 101 table 25. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 26. typical and maximum current consumption in sl eep mode . . . . . . . . . . . . . . . . . . . . . . . 103 table 27. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . 104 table 28. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . 105 table 29. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . 105 table 30. typical current consumption in run mo de, code with data processing running from flash memory or ram, regulator on (art accelerator enabled except prefetch), vdd=1.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 31. typical current consumption in run mode, code with data processing running from flash memory, regulator off (art accelerator enabled except prefetch). . . . . . . 108 table 32. typical current consumption in sleep mode, regulator on, vdd=1.7 v . . . . . . . . . . . . . 109 table 33. tyical current consumption in sleep mode, regula tor off. . . . . . . . . . . . . . . . . . . . . . . . 110 table 34. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 35. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 36. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 37. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 38. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 39. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 40. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 41. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 42. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 43. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 list of tables stm32f437xx and stm32f439xx 8/240 docid024244 rev 10 table 44. plli2s (audio pll) characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 25 table 45. pllisai (audio and lcd-tft pll) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 46. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 47. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 48. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 49. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 50. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 51. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 52. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 53. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 table 54. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 55. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 56. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 57. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 58. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 59. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 60. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 61. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 62. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 63. i 2 s dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 64. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 65. usb otg full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 51 table 66. usb otg full speed dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 67. usb otg full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 68. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 table 69. usb hs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 table 70. dynamic characteristics: usb ulpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 71. dynamics characteristics: ethe rnet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . 155 table 72. dynamics characteristics: ethe rnet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . 156 table 73. dynamics characteristics: ethe rnet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 74. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 75. adc static accuracy at f adc = 18 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 76. adc static accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 77. adc static accuracy at f adc = 36 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 78. adc dynamic accuracy at f adc = 18 mhz - limited test conditions . . . . . . . . . . . . . . . . . 160 table 79. adc dynamic accuracy at f adc = 36 mhz - limited test conditions . . . . . . . . . . . . . . . . . 160 table 80. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 table 81. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 82. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 83. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 84. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 85. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 86. asynchronous non-multiplexed sram/psram/nor - read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 87. asynchronous non-multiplexed sram/psram/nor read - nwait timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 88. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 172 table 89. asynchronous non-multiplexed sram/psram/nor write - nwait timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 90. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 91. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 174 table 92. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 175 docid024244 rev 10 9/240 stm32f437xx and stm32f439xx list of tables 9 table 93. asynchronous multiplexed psram/nor write-nwai t timings . . . . . . . . . . . . . . . . . . . . 176 table 94. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 95. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 96. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 180 table 97. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 98. switching characteristics for pc card/cf read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 99. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 100. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 101. switching characteristics for nand flash write cycl es. . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 102. sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 103. lpsdr sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 91 table 104. sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 105. lpsdr sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 106. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 107. ltdc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 108. dynamic characteristics: sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 109. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 110. lqpf100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 200 table 111. wlcsp143 - 143-ball, 4.521x 5. 547 mm, 0.4 mm pitch wa fer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 table 112. wlcsp143 recommended pcb design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 205 table 113. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 114. lqfp176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 115. lqfp208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 116. ufbga169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 117. ufbga169 recommended pcb design rules (0 .5 mm pitch bga) . . . . . . . . . . . . . . . . . 219 table 118. ufbga176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 119. ufbga176+25 recommended pcb design rules (0.65 mm pitch bga) . . . . . . . . . . . . . 222 table 120. tfbga216 - 216 ball 13 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 121. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 122. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 123. limitations depending on the operating power su pply range . . . . . . . . . . . . . . . . . . . . . . 228 table 124. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 list of figures stm32f437xx and stm32f439xx 10/240 docid024244 rev 10 list of figures figure 1. compatible board design stm32f10xx/stm32f2xx/stm32f4xx for lqfp100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 2. compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. compatible board design between stm32f2xx and stm32f4xx for lqfp176 and ufbga176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. stm32f437xx and stm32f439xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. stm32f437xx and stm32f439xx multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 26 figure 7. pdr_on control with internal re set off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10. startup in re gulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 30 figure 11. stm32f43x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12. stm32f43x wlcsp143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 figure 13. stm32f43x lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 14. stm32f43x lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 15. stm32f43x lqfp208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 16. stm32f43x ufbga169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 figure 17. stm32f43x ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 18. stm32f43x tfbga216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 19. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 20. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 21. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 22. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 23. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 24. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 25. typical v bat current consumption (lse and rtc on/backup ram off) . . . . . . . . . . . 106 figure 26. typical v bat current consumption (lse and rtc on/backup ram on) . . . . . . . . . . . . 106 figure 27. high-speed external clock source ac timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 28. low-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 29. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1 figure 30. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 31. acchsi accuracy versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 32. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 33. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 34. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 35. ft i/o input ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 36. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 37. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 38. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 39. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 40. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 46 figure 41. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 42. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 43. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 docid024244 rev 10 11/240 stm32f437xx and stm32f439xx list of figures 12 figure 44. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 45. usb otg full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 152 figure 46. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 47. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 48. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 49. ethernet mii timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 50. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 51. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 52. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 163 figure 53. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 164 figure 54. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 55. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 170 figure 56. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 172 figure 57. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 173 figure 58. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 175 figure 59. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 60. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 61. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 62. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 63. pc card/compactflash controller waveforms for common me mory read access . . . . . . 183 figure 64. pc card/compactflash controller waveforms for common me mory write access . . . . . . 183 figure 65. pc card/compactflash contro ller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 66. pc card/compactflash cont roller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 67. pc card/compactflash cont roller waveforms for i/o space read access . . . . . . . . . . . . 185 figure 68. pc card/compactflash cont roller waveforms for i/o space write access . . . . . . . . . . . . 186 figure 69. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 70. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 71. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 189 figure 72. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 189 figure 73. sdram read access waveforms (c l = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 figure 74. sdram write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 figure 75. dcmi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 76. lcd-tft horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 96 figure 77. lcd-tft vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 78. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 79. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 80. lqfp100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 199 figure 81. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 82. lqfp100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 83. wlcsp143 - 143-ball, 4.521x 5. 547 mm, 0.4 mm pitch wa fer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 84. wlcsp143 - 143-ball, 4.521x 5. 547 mm, 0.4 mm pitch wa fer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 85. wlcsp143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 86. lqfp144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 206 figure 87. lqpf144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 88. lqfp144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 89. lqfp176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 210 list of figures stm32f437xx and stm32f439xx 12/240 docid024244 rev 10 figure 90. lqfp176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 212 figure 91. lqfp176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 92. lqfp208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 214 figure 93. lqfp208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 94. lqfp208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 95. ufbga169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 96. ufbga169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 97. ufbga169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 98. ufbga176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 99. ufbga176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 100. ufbga176+25 marking example (package top view ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 101. tfbga216 - 216 ball 13 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 figure 102. tfbga176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 103. usb controller configured as peripheral-only and used in full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 29 figure 104. usb controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 229 figure 105. usb controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 230 figure 106. usb controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 107. mii mode using a 25 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 figure 108. rmii with a 50 mhz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 figure 109. rmii with a 25 mhz crystal and phy with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 docid024244 rev 10 13/240 stm32f437xx and stm32f439xx introduction 43 1 introduction this datasheet provides the description of the stm32f437xx and stm32f439xx line of microcontrollers. for more details on the whole stmicroelectronics stm32 family, please refer to section 2.1: full compatibilit y throughout the family . the stm32f437xx and stm32f439xx datasheet should be read in conjunction with the stm32f4xx reference manual. for information on the cortex ? -m4 core, please refer to the cortex ? -m4 programming manual (pm0214), available from www.st.com . description stm32f437xx and stm32f439xx 14/240 docid024244 rev 10 2 description the stm32f437xx and stm32f439xx devices are based on the high-performance arm ? cortex ? -m4 32-bit risc core operating at a fr equency of up to 180 mhz. the cortex-m4 core features a floating point unit (fpu) single precision which supports all arm ? single- precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances application security. the stm32f437xx and stm32f439xx devices incorporate high-speed embedded memories (flash memory up to 2 mbyte, up to 256 kbytes of sram), up to 4 kbytes of backup sram, and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb buses and a 32 -bit multi-ahb bus matrix. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for mo tor control, two general-purpose 32-bit timers, a true random number generator (rng) and a cryptographic acceleration cell. they also feature standard and advanced communication interfaces. ? up to three i 2 cs ? six spis, two i 2 ss full duplex. to achieve audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. ? four usarts plus four uarts ? an usb otg full-spee d and a usb otg high- speed with full-speed capability (with the ulpi), ? two cans ? one sai serial audio interface ? an sdio/mmc interface ? ethernet and camera interface ? lcd-tft display controller ? chrom-art accelerator?. advanced peripherals include an sdio, a flexible memory control (fmc) interface, a camera interface for cmos sensors and a cryptographic acceleration cell. refer to table 2: stm32f437xx and stm32f439xx features and peripheral counts for the list of peripherals available on each part number. the stm32f437xx and stm32f439xx devices oper ates in the ?40 to +105 c temperature range from a 1.7 to 3.6 v power supply. the supply voltage can drop to 1.7 v with the use of an external power supply supervisor (refer to section 3.17.2: in ternal reset off ). a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f437xx and stm32f439xx devices offer devices in 8 packages ranging from 100 pins to 216 pins. the set of included pe ripherals changes with the device chosen. description stm32f437xx and stm32f439xx 15/240 docid024244 rev 10 these features make the stm32f437xx and stm32f439xx micr ocontrollers suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances figure 4 shows the general block diagram of the device family. table 2. stm32f437xx and stm32f439xx features and peripheral counts peripherals stm32f437 vx stm32f439 vx stm32f437zx stm32f437ai stm32f439ai stm32f439zx s tm32f437ix stm32f439ix stm32f439bx stm32f439nx flash memory in kbytes 1024 2048 1024 2048 1024 2048 2048 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 sram in kbytes system 256(112+16+64+64) backup 4 fmc memory controller yes (1) ethernet yes timers general- purpose 10 advance d-control 2 basic 2 random number generator yes stm32f437xx and stm32f439xx description docid024244 rev 10 16/240 communication interfaces spi / i 2 s 4/2 (full duplex) (2) 6/2 (full duplex) (2) i 2 c 3 usart/ uart 4/4 usb otg fs yes usb otg hs yes can 2 sai 1 sdio yes camera interface yes lcd-tft no yes no yes yes no yes chrom-art accelerator? (dma2d) yes cryptography yes gpios 82 114 140 168 168 12-bit adc number of channels 3 16 24 12-bit dac number of channels yes 2 maximum cpu frequency 180 mhz operating voltage 1.7 to 3.6 v (3) operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp100 wlcsp143 lqfp144 ufbga169 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216 1. for the lqfp100 package, only fmc bank1 or bank2 are available. bank1 can only support a multiplexed nor/psram memory using t he ne1 chip select. bank2 can only support a 16- or 8-bit nand flash memory using the nce2 chip select. the interrupt line cannot be used since port g is no t available in this package. 2. the spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio mode. 3. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.17.2: internal reset off ). table 2. stm32f437xx and stm32f439xx features and peripheral counts (continued) peripherals stm32f437 vx stm32f439 vx stm32f437zx stm32f437ai stm32f439ai stm32f439zx s tm32f437ix stm32f439ix stm32f439bx stm32f439nx docid024244 rev 10 17/240 stm32f437xx and stm32f439xx description 43 2.1 full compatibility throughout the family the stm32f437xx and stm32f439xx devices are part of the stm32f4 family. they are fully pin-to-pin, software and feature compatible with the stm32f2xx devices, allowing the user to try different memory densities, peripherals, and performances (fpu, higher frequency) for a greater degree of freedom during the development cycle. the stm32f437xx and stm32f 439xx devices maintain a close compatibility with the whole stm32f10xx family. all functional pins are pin-to-pin compatible. the stm32f437xx and stm32f439xx, however, are not drop-in replacements for the stm32f10xx devices: the two families do not have th e same power scheme, and so th eir power pins are different. nonetheless, transition from the stm32f10xx to the stm32f43x family remains simple as only a few pins are impacted. figure 1 , figure 2 , and figure 3 , give compatible board designs between the stm32f4xx, stm32f2xx, and st m32f10xx families. figure 1. compatible board design stm32f10xx/stm32f2xx/stm32f4xx for lqfp100 package d l g 9 6 6 9 6 6 9 ' ' 9 6 6 9 6 6 9 6 6 ? u h v l v w r u r u v r o g h u l q j e u l g j h s u h v h q w i r u w k h 6 7 0 ) [ [ [ f r q i l j x u d w l r q q r w s u h v h q w l q w k h 6 7 0 ) [ [ f r q i l j x u d w l r q 9 6 6 9 6 6 7 z r ? u h v l v w r u v f r q q h f w h g w r 9 6 6 i r u w k h 6 7 0 ) [ [ 9 6 6 i r u w k h 6 7 0 ) [ [ 9 6 6 r u 1 & i r u w k h 6 7 0 ) [ [ 9 6 6 i r u 6 7 0 ) [ [ 9 ' ' i r u 6 7 0 ) [ [ description stm32f437xx and stm32f439xx 18/240 docid024244 rev 10 figure 2. compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package figure 3. compatible board design between stm32f2xx and stm32f4xx for lqfp176 and ufbga176 packages d l g 9 6 6 ? u h v l v w r u r u v r o g h u l q j e u l g j h s u h v h q w i r u w k h 6 7 0 ) [ [ f r q i l j x u d w l r q q r w s u h v h q w l q w k h 6 7 0 ) [ [ f r q i l j x u d w l r q 9 6 6 7 z r ? u h v l v w r u v f r q q h f w h g w r 9 6 6 i r u w k h 6 7 0 ) [ [ 9 6 6 9 ' ' r u 1 & i r u w k h 6 7 0 ) [ [ 9 ' ' r u v l j q d o i u r p h [ w h u q d o s r z h u v x s s o \ v x s h u y l v r u i r u w k h 6 7 0 ) [ [ 9 6 6 9 ' ' 9 6 6 9 6 6 3 ' 5 b 2 1 9 6 6 9 ' ' 9 6 6 i r u 6 7 0 ) [ [ 9 ' ' i r u 6 7 0 ) [ [ 6 l j q d o i u r p h [ w h u q d o s r z h u v x s s o \ v x s h u y l v r u 1 r w s r s x o d w h g z k h q ? u h v l v w r u r u v r o g h u l q j e u l g j h s u h v h q w 1 r w s r s x o d w h g i r u 6 7 0 ) [ [ 0 6 9 7 z r ? u h v l v w r u v f r q q h f w h g w r 9 6 6 9 ' ' r u 1 & i r u w k h 6 7 0 ) [ [ 9 ' ' r u v l j q d o i u r p h [ w h u q d o s r z h u v x s s o \ v x s h u y l v r u i r u w k h 6 7 0 ) [ [ 3 ' 5 b 2 1 9 6 6 9 ' ' 6 l j q d o i u r p h [ w h u q d o s r z h u v x s s o \ v x s h u y l v r u * 1 ' i r u 6 7 0 ) [ [ % < 3 $ 6 6 b 5 ( * i r u 6 7 0 ) [ [ docid024244 rev 10 19/240 stm32f437xx and stm32f439xx description 43 figure 4. stm32f437xx and stm32f439xx block diagram 1. the timers connected to apb2 are clocke d from timxclk up to 180 mhz, while the timers connected to apb1 are clocked from timxclk either up to 90 mhz or 180 mhz depending on timpre bit configuration in the rcc_dckcfgr register. 2. the lcd-tft is available only on stm32f439xx devices. ' 0 ) / 0 / 2 4 ! ! ( " ! 0 " % 8 4 ) 4 7 + 5 0 ! & 0 ! ; = 4 ) - 0 7 - c o m p l c h a n 4 ) - ? # ( ; = . c h a n 4 ) - ? # ( ; = % 4 2 " + ) . a s ! & 5 3 ! 2 4 2 8 4 8 # + # 4 3 2 4 3 a s ! & 3 0 ) - / 3 ) - ) 3 / 3 # + . 3 3 a s ! & ! 0 " - ( z ! 0 " - ( z a n a l o g i n p u t s c o m m o n t o t h e ! $ # s 6 $ $ 2 % & ? ! $ # 5 ! 2 4 - / 3 ) 3 $ - ) 3 / 3 $ ? e x t 3 # + # + . 3 3 7 3 - # + a s ! & 3 0 ) 3 4 8 2 8 b x # ! . $ ! # ? / 5 4 a s ! & ) 4 & 7 7 $ ' + " " + 0 3 2 ! - / 3 # ? ) . / 3 # ? / 5 4 6 $ $ ! 6 3 3 ! . 2 3 4 s m c a r d i r $ ! b 3 $ ) / - - # $ ; = # - $ # + a s ! & 6 " ! 4 t o 6 $ - ! 3 # , 3 $ ! 3 - " ! a s ! & ) # 3 - " 5 3 * 4 ! ' 3 7 ! 2 - # o r t e x - - ( z . 6 ) # % 4 - - 0 5 4 2 ! # % # , + 4 2 ! # % $ ; = % t h e r n e t - ! # $ - ! & ) & / - ) ) o r 2 - ) ) a s ! & - $ ) / a s ! & 5 3 " / 4 ' ( 3 $ 0 $ - 5 , 0 ) # + $ ; = $ ) 2 3 4 0 . 8 4 ) $ 6 " 5 3 3 / & $ - ! 3 t r e a m s & ) & / ! 2 4 ! # # % , # ! # ( % 3 2 ! - + " # , + . % ; = ! ; = $ ; = . / % . . 7 % . . " , ; = 3 $ # , + % ; = 3 $ . % ; = 3 $ . 7 % . , . 7 ! ) 4 . ) / 2 $ . 2 % ' # $ ) . 4 2 2 . ' # a m e r a i n t e r f a c e ( 3 9 . # 6 3 9 . # 0 5 ) 8 # , + $ ; = 0 ( 9 5 3 " / 4 ' & 3 $ 0 $ - ) $ 6 " 5 3 3 / & & ) & / ! ( " - ( z 0 ( 9 & ) & / 5 3 ! 2 4 - " p s 4 e m p e r a t u r e s e n s o r ! $ # ! $ # ! $ # ) & ) & 6 $ $ ! 6 $ $ ! 0 / 2 0 $ 2 " / 2 3 u p p l y s u p e r v i s i o n 6 $ $ ! 0 6 $ ) n t 0 / 2 r e s e t 8 4 ! , k ( z - ! . ! ' 4 2 4 # 2 # ( 3 2 # , 3 3 t a n d b y i n t e r f a c e ) 7 $ ' 6 " ! 4 6 $ $ ! 6 $ $ ! 7 5 2 e s e t c l o c k c o n t r o l 0 , , 0 # , + x 6 $ $ t o 6 6 3 3 6 # ! 0 6 # ! 0 6 o l t a g e r e g u l a t o r t o 6 6 $ $ 0 o w e r m a n a g m t 6 $ $ " a c k u p r e g i s t e r ! ( " b u s m a t r i x 3 - ! 0 " - ( z , 3 4 ) - 4 ) - c h a n n e l s a s ! & $ ! # $ ! # - " & l a s h % x t e r n a l m e m o r y c o n t r o l l e r & - # 3 2 ! - 3 $ 2 ! - 0 3 2 ! - . / 2 & l a s h 0 # # a r d . ! . $ & l a s h 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - $ " 5 3 - 3 6 & ) & / & 0 5 ! 0 " - ( z m a x 3 2 ! - + " # # - d a t a 2 ! - + " ! ( " ! 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( : functional overview stm32f437xx and stm32f439xx 20/240 docid024244 rev 10 3 functional overview 3.1 arm ? cortex ? -m4 with fpu and embe dded flash and sram the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu core is a 32-bit risc processor that features exceptional code-efficiency, delivering the high-performanc e expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit ) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f43x family is compatible with all arm tools and software. figure 4 shows the general block diagram of the stm32f43x family. note: cortex-m4 with fpu co re is binary compatible with the cortex-m3 core. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 with fpu processors. it balances the inherent performance advantage of the arm ? cortex ? -m4 with fpu over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 225 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 180 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. docid024244 rev 10 21/240 stm32f437xx and stm32f439xx functional overview 43 3.4 embedded flash memory the devices embed a flash memory of up to 2 mbytes available for storing programs and data. 3.5 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the c rc calculation unit help s compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 embedded sram all devices embed: ? up to 256kbytes of system sram includin g 64 kbytes of ccm (core coupled memory) data ram ram memory is accessed (read/write) at cpu clock speed with 0 wait states. ? 4 kbytes of backup sram this area is accessible only from the cpu. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 3.7 multi-ahb bus matrix the 32-bit multi-ahb bu s matrix interconnects all the ma sters (cpu, dmas, ethernet, usb hs, lcd-tft, and dma2d) and the slaves (flash memory, ram, fmc, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. functional overview stm32f437xx and stm32f439xx 22/240 docid024244 rev 10 figure 5. stm32f437xx and stm32f439xx multi-ahb matrix 3.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. $ 5 0 & r u w h [ 0 * 3 ' 0 $ * 3 ' 0 $ 0 $ & ( w k h u q h w 8 6 % 2 7 * + 6 % x v p d w u l [ 6 , & 2 ' ( ' & 2 ' ( $ & & ( / ) o d v k p h p r u \ 6 5 $ 0 . e \ w h 6 5 $ 0 . e \ w h $ + % s h u l s k h u d o v $ + % s h u l s k h u d o v ) 0 & h [ w h u q d o 0 h p & w o , e x v ' e x v 6 e x v ' 0 $ b 3 , ' 0 $ b 0 ( 0 ' 0 $ b 0 ( 0 ' 0 $ b 3 ( 7 + ( 5 1 ( 7 b 0 8 6 % b + 6 b 0 - 3 6 & & 0 g d w d 5 $ 0 . e \ w h $ 3 % $ 3 % 6 5 $ 0 . e \ w h / & ' 7 ) 7 & k u r p $ 5 7 $ f f h o h u d w r u ' 0 $ ' / & ' 7 ) 7 b 0 ' 0 $ ' docid024244 rev 10 23/240 stm32f437xx and stm32f439xx functional overview 43 the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? dac ? sdio ? cryptographic acceleration ? camera interface (dcmi) ? adc ? sai1. 3.9 flexible memory controller (fmc) all devices embed an fmc. it has four chip select outputs supporting the following modes: pccard/compact flash, sdram/lpsdr sd ram, sram, psram, nor flash and nand flash. functionality overview: ? 8-,16-, 32-bit data bus width ? read fifo for sdram controller ? write fifo ? maximum fmc_clk/fmc_sdcl k frequency for synchron ous accesses is 90 mhz. lcd parallel interface the fmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 lcd-tft controller (ava ilable only on stm32f439xx) the lcd-tft display controller provides a 24-b it parallel digital rgb (red, green, blue) and delivers all signals to interface directly to a broad range of lcd and tft panels up to xga (1024x768) resolution with the following features: ? 2 displays layers with dedicated fifo (64x32-bit) ? color look-up table (clut) up to 256 colors (256x24-bit) per layer ? up to 8 input color formats selectable per layer ? flexible blending between two layers us ing alpha value (per pixel or constant) ? flexible programmable parameters for each layer ? color keying (transparency color) ? up to 4 programmable interrupt events. functional overview stm32f437xx and stm32f439xx 24/240 docid024244 rev 10 3.11 chrom-art accelerator? (dma2d) the chrom-art accelerator? (dma2d) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conv ersion. it supports the following functions: ? rectangle filling with a fixed color ? rectangle copy ? rectangle copy with pixel format conversion ? rectangle composition with blending and pixel format conversion. various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. it embeds dedicated memory to store color lookup tables. an interrupt can be generated when an operation is complete or at a programmed watermark. all the operations are fully automatized and are running independently from the cpu or the dmas. 3.12 nested vectored inter rupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m4 with fpu core. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 3.13 external interrupt/ event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 168 gpios can be connected to the 16 external interrupt lines. 3.14 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-tr immed to offer 1% accuracy over the full temperature range . the application can then select as system clo ck either the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a failure is docid024244 rev 10 25/240 stm32f437xx and stm32f439xx functional overview 43 detected, the system automatically switches back to the internal rc oscillator and a software interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 180 mhz. simila rly, full interrupt ma nagement of the pll clock entry is available when necessary (for ex ample if an indirectly us ed external oscillator fails). several prescalers allow t he configuration of the two ahb buses, the high-speed apb (apb2) and the low-sp eed apb (apb1) domains. the maxi mum frequency of the two ahb buses is 180 mhz while th e maximum frequency of the high-speed apb domains is 90 mhz. the maximum allowe d frequency of the low-sp eed apb domain is 45 mhz. the devices embed a dedicated pll (plli2s) and pllsai which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. 3.15 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory through a serial interface. refer to application note an2606 for details. 3.16 power supply schemes ? v dd = 1.7 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. note: v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.17.2: internal reset off ). refer to table 3: voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. 3.17 power supply supervisor 3.17.1 internal reset on on packages embedding the pdr_on pin, th e power supply supervisor is enabled by holding pdr_on high. on the other package, the power supply supervisor is always enabled. the device has an integrated power-on reset (por)/ power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por/pdr is always active and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is functional overview stm32f437xx and stm32f439xx 26/240 docid024244 rev 10 reached, the option byte loading process star ts, either to confirm or modify default bor thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.17.2 internal reset off this feature is available only on packages featuring the pdr_on pin. the internal power-on reset (por) / power-down reset (pdr) circui try is disabled through the pdr_on pin. an external power supply supervisor should monitor v dd and should maintain the device in reset mode as long as v dd is below a specified threshold. pdr_on should be connected to this external power supply supervisor. refer to figure 6: power supply supervisor interconnection with internal reset off . figure 6. power supply supervisor interconnection with internal reset off the v dd specified threshold, below which the device must be maintained under reset, is 1.7 v (see figure 7 ). a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no more supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled ? the brownout reset (bor) circuitry must be disabled ? the embedded programmable voltage detector (pvd) is disabled ? v bat functionality is no more available and v bat pin should be connected to v dd . all packages, except for the lqfp100, allow to disable the internal reset through the pdr_on signal. 0 6 9 1 5 6 7 9 ' ' 3 ' 5 b 2 1 ( [ w h u q d o 9 ' ' s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 ' ' 9 9 ' ' $ s s o l f d w l r q u h v h w v l j q d o r s w l r q d o docid024244 rev 10 27/240 stm32f437xx and stm32f439xx functional overview 43 figure 7. pdr_on control with internal reset off 3.18 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down ? regulator off 3.18.1 regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all ot her packages, the regula tor is always enabled. there are three power modes configured by software when the regulator is on: ? mr mode used in run/sleep modes or in stop modes ? in run/sleep mode the mr mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. 0 6 9 9 ' ' w l p h 3 ' 5 9 w l p h 1 5 6 7 3 ' 5 b 2 1 3 ' 5 b 2 1 5 h v h w e \ r w k h u v r x u f h w k d q s r z h u v x s s o \ v x s h u y l v r u functional overview stm32f437xx and stm32f439xx 28/240 docid024244 rev 10 the over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. ? in stop modes the mr can be configured in two ways during stop mode: mr operates in normal mode (default mode of mr in stop mode) mr operates in under-drive mode (reduced leakage mode). ? lpr is used in the stop modes: the lp regulator mode is configured by software when entering stop mode. like the mr mode, the lpr can be configured in two ways during stop mode: ? lpr operates in normal mode (default mode when lpr is on) ? lpr operates in under-drive mode (reduced leakage mode). ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost. refer to table 3 for a summary of voltage regulator modes versus device operating modes. two external ceramic capacitors should be connected on v cap_1 and v cap_2 pin. refer to figure 22: power supply scheme and table 19: vcap1/vcap2 operating conditions . all packages have the regulator on feature. 3.18.2 regulator off this feature is availa ble only on packages fe aturing the bypass_reg pi n. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v 12 voltage source through v cap_1 and v cap_2 pins. since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. refer to table 17: general operating conditions .the two 2.2 f ceramic capacitors should be replaced by two 100 nf decoupling capacitors. refer to figure 22: power supply scheme . when the regulator is off, there is no more internal monitoring on v 12 . an external power supply supervisor should be used to monitor the v 12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v 12 power domain. table 3. voltage regulator configuration mode versus device operating mode (1) 1. ?-? means that the corresponding configuration is not available. voltage regulator configuration run mode sleep mode stop mode standby mode normal mode mr mr mr or lpr - over-drive mode (2) 2. the over-drive mode is not available when v dd = 1.7 to 2.1 v. mr mr - - under-drive mode - - mr or lpr - power-down mode ---yes docid024244 rev 10 29/240 stm32f437xx and stm32f439xx functional overview 43 in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin sinc e it allows to reset a part of the v 12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required. ? the over-drive and under-drive modes are not available. ? the standby mode is not available. figure 8. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.7 v, then pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.7 v (see figure 9 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.7 v, then pa0 could be asserted low externally (see figure 10 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application (see table 17: general operating conditions ). d l 9 % < 3 $ 6 6 b 5 ( * 9 & $ 3 b 9 & $ 3 b 3 $ 9 9 ' ' 1 5 6 7 9 ' ' $ s s o l f d w l r q u h v h w v l j q d o r s w l r q d o ( [ w h u q d o 9 & $ 3 b s r z h u v x s s o \ v x s h u y l v r u ( [ w u h v h w f r q w u r o o h u d f w l y h z k h q 9 & $ 3 b 0 l q 9 9 functional overview stm32f437xx and stm32f439xx 30/240 docid024244 rev 10 figure 9. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). figure 10. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). d l i 9 ' ' w l p h 0 l q 9 3 ' 5 9 r u 9 9 & $ 3 b 9 & $ 3 b 9 1 5 6 7 w l p h 9 ' ' w l p h 0 l q 9 9 & $ 3 b 9 & $ 3 b 9 3 $ d v v h u w h g h [ w h u q d o o \ 1 5 6 7 w l p h d l h 3 ' 5 9 r u 9 docid024244 rev 10 31/240 stm32f437xx and stm32f439xx functional overview 43 3.18.3 regulator on/off and inte rnal reset on/off availability 3.19 real-time clock (r tc), backup sram an d backup registers the backup domain includes: ? the real-time clock (rtc) ? 4 kbytes of backup sram ? 20 backup registers the real-time clock (rtc) is an independent bc d timer/counter. dedica ted registers contain the second, minute, hour (in 12/24 hour), we ek day, date, month, year, in bcd (binary- coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensa te for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base cl ock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the 4-kbyte backup sram is an eeprom-like memory area. it can be used to store data which need to be retained in vbat and standby mode. this memory area is disabled by default to minimize power consumption (see section 3.20: low-power modes ). it can be enabled by software. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 3.20: low-power modes ). table 4. regulator on/off and in ternal reset on/off availability package regulator on regulator off internal reset on internal reset off lqfp100 yes no yes no lqfp144, lqfp208 yes pdr_on set to v dd yes pdr_on connected to an external power supply supervisor wlcsp143, lqfp176, ufbga169, ufbga176, tfbga216 yes bypass_reg set to v ss yes bypass_reg set to v dd functional overview stm32f437xx and stm32f439xx 32/240 docid024244 rev 10 additional 32-bit registers contain the prog rammable alarm subseconds, seconds, minutes, hours, day, and date. like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. 3.20 low-power modes the devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal osc illators are disabled. the voltage regulator can be put either in main regulator mode (mr) or in low-power mode (lpr). both modes can be configured as follows (see table 5: voltage regulator modes in stop mode ): ? normal mode (default mode when mr or lpr is enabled) ? under-drive mode. the device can be woken up from the stop mo de by any of the exti line (the exti line source can be one of the 16 external lines , the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. the standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. table 5. voltage regulator modes in stop mode voltage regulator configuration main regulator (mr) low-power regulator (lpr) normal mode mr on lpr on under-drive mode mr in under-dri ve mode lpr in under-drive mode docid024244 rev 10 33/240 stm32f437xx and stm32f439xx functional overview 43 3.21 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is not connected to v dd (internal reset off), the v bat functionality is no more available and v bat pin should be connected to v dd . 3.22 timers and watchdogs the devices include two advanced-control time rs, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. table 6 compares the features of the advanced-c ontrol, general-purpose and basic timers. functional overview stm32f437xx and stm32f439xx 34/240 docid024244 rev 10 table 6. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary output max interface clock (mhz) max timer clock (mhz) (1) advanced -control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 90 180 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 45 90/180 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 45 90/180 tim9 16-bit up any integer between 1 and 65536 no 2 no 90 180 tim10 , tim11 16-bit up any integer between 1 and 65536 no 1 no 90 180 tim12 16-bit up any integer between 1 and 65536 no 2 no 45 90/180 tim13 , tim14 16-bit up any integer between 1 and 65536 no 1 no 45 90/180 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 45 90/180 1. the maximum timer clock is either 90 or 180 mhz depending on timpre bit configuration in the rcc_dckcfgr register. docid024244 rev 10 35/240 stm32f437xx and stm32f439xx functional overview 43 3.22.1 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output if configured as standard 16-bit timers, they ha ve the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 and tim8 support indepe ndent dma request generation. 3.22.2 general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f43x devices (see table 6 for differences). ? tim2, tim3, tim4, tim5 the stm32f43x include 4 full-featured g eneral-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/ou tput compare, pwm or one-pul se mode output. this gives up to 16 input capture/output comp are/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanc ed-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have indepen dent dma request generation. they are capable of handling quadrature (incremental ) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10, tim11, ti m12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels fo r input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. 3.22.3 basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support indepe ndent dma request generation. functional overview stm32f437xx and stm32f439xx 36/240 docid024244 rev 10 3.22.4 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 3.22.5 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.22.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. 3.23 inter-integrated circuit interface ( i 2 c) up to three i2c bus interfaces can operate in multimaster and slave modes. they can support the standard (up to 100 khz), and fa st (up to 400 khz) modes. they support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. the devices also include programmable analog and digital noise filters (see table 7 ). 3.24 universal synchronous/asynch ronous receiver transmitters (usart) the devices embed four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and four universal asynchronous receiver transmitters (uart4, uart5, uart7, and uart8). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and u sart6 interfaces are able to table 7. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks docid024244 rev 10 37/240 stm32f437xx and stm32f439xx functional overview 43 communicate at speeds of up to 11.25 mbit/s . the other available in terfaces communicate at up to 5.62 bit/s. usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interf aces can be served by the dma controller. 3.25 serial peripheral interface (spi) the devices feature up to six spis in slave and master modes in full-duplex and simplex communication modes. spi1, spi4, spi5, and spi6 can communicate at up to 45 mbits/s, spi2 and spi3 can communicate at up to 22.5 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card /mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operat e in ti mode for comm unications in master mode and slave mode. table 8. usart feature comparison (1) usart name standard features modem (rts/cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 5.62 11.25 apb2 (max. 90 mhz) usart2 x x x x x x 2.81 5.62 apb1 (max. 45 mhz) usart3 x x x x x x 2.81 5.62 apb1 (max. 45 mhz) uart4 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) uart5 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) usart6 x x x x x x 5.62 11.25 apb2 (max. 90 mhz) uart7 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) uart8 x - x - x - 2.81 5.62 apb1 (max. 45 mhz) 1. x = feature supported. functional overview stm32f437xx and stm32f439xx 38/240 docid024244 rev 10 3.26 inter-integr ated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i2sx can be served by the dma controller. note: for i2s2 full-duplex mode, i2s2_ck and i2s2_ws signals can be used only on gpio port b and gpio port d. 3.27 serial audio interface (sai1) the serial audio interface ( sai1) is based on two independe nt audio sub-blocks which can operate as transmitter or receiver with their fifo. many audio protocols are supported by each block: i2s standards, lsb or msb-justified, pcm/dsp, tdm, ac?97 and spdif output, supporting audio sampling frequencies from 8 khz up to 192 khz. both sub-blocks can be configured in master or in slave mode. in master mode, the master clock can be output to the external dac/codec at 256 times of the sampling frequency. the two sub-blocks can be configured in synchronous mode when full-duplex mode is required. sai1 can be served by the dma controller. 3.28 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s and sai applications. it allows to achieve error-free i 2 s sampling clock accuracy witho ut compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s/sai sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i 2 s/sai flow with an external pll (or codec output). 3.29 audio and lcd pll(pllsai) an additional pll dedicated to audio and l cd-tft is used for sai1 peripheral in case the plli2s is programmed to achieve another audio sampling frequency (49.152 mhz or 11.2896 mhz) and the audio application requi res both sampling frequencies simultaneously. the pllsai is also used to generate the lcd-tft clock. docid024244 rev 10 39/240 stm32f437xx and stm32f439xx functional overview 43 3.30 secure digital input/ output interface (sdio) an sd/sdio/mmc host interface is availabl e, that supports multimediacard system specification version 4.2 in three different da tabus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdi o/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 3.31 ethernet mac interface with dedicated dma and ieee 1588 support the devices provide an ieee- 802.3-2002-compliant media access controller (mac) for ethernet lan communications through an industry-standard medium-independent interface (mii) or a reduced medium-independent interfac e (rmii). the microcontroller requires an external physical interface device (phy) to co nnect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connec ted to the device mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) from the microcontroller. the devices include the following features: ? supports 10 and 100 mbit/s rates ? dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f4xx reference manual for details) ? tagged mac frame support (vlan support) ? half-duplex (csma/cd) and full-duplex operation ? mac control sublayer (control frames) support ? 32-bit crc generation and removal ? several address filtering modes for physic al and multicast address (multicast and group addresses) ? 32-bit status code for each transmitted or received frame ? internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes. ? supports hardware ptp (precision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp compar ator connected to the tim2 input ? triggers interrupt when system time becomes greater than target time 3.32 controller area network (bxcan) the two cans are compliant with the 2.0a and b (a ctive) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit id entifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive functional overview stm32f437xx and stm32f439xx 40/240 docid024244 rev 10 fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. 3.33 universal serial bus on -the-go full-speed (otg_fs) the devices embed an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillato r. the major features are: ? combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 4 bidirectional endpoints ? 8 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 3.34 universal serial bus on -the-go high-speed (otg_hs) the devices embed a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external phy device connecte d to the ulpi is required. the usb otg hs peripheral is compliant wit h the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll co nnected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 1 kbit 35 with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 6 bidirectional endpoints ? 12 host channels with periodic out support ? internal fs otg phy support ? external hs or hs otg operation suppor ting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. ? internal usb dma ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected docid024244 rev 10 41/240 stm32f437xx and stm32f439xx functional overview 43 3.35 digital camera interface (dcmi) the devices embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 54 mbyte/s at 54 mhz. it features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image 3.36 cryptograp hic acceleration the devices embed a cryptographic accelerator. this cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data in tegrity and non repudiation when exchanging messages with a peer. ? these algorithms consists of: encryption/decryption ? des/tdes (data encryption standard/triple data encryption standard): ecb (electronic codebook) and cbc (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key ? aes (advanced encryption standard): ecb, cbc, gcm, ccm, and ctr (counter mode) chaining algorithms, 128, 192 or 256-bit key universal hash ? sha-1 and sha-2 (secure hash algorithms) ?md5 ?hmac the cryptographic accelerator supports dma request generation. 3.37 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit. 3.38 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. functional overview stm32f437xx and stm32f439xx 42/240 docid024244 rev 10 fast i/o handling a llowing maximum i/o toggling up to 90 mhz. 3.39 analog-to-digital converters (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer. 3.40 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the same input channel as v bat , adc1_in18, which is used to convert the sensor output voltage into a digital value. when the temperature sensor and v bat conversion are enabled at the same time, only v bat conversion is performed. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.41 digital-to-analog converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 10-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ docid024244 rev 10 43/240 stm32f437xx and stm32f439xx functional overview 43 eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 3.42 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.43 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f43x through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools. pinouts and pin description stm32f437xx and stm32f439xx 44/240 docid024244 rev 10 4 pinouts and pin description figure 11. stm32f43x lqfp100 pinout 1. the above figure shows the package top view. 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # 0 # 6 3 3 6 $ $ 0 ( . 2 3 4 0 # 0 # 0 # 0 # 6 $ $ 6 3 3 ! 6 2 % & 6 $ $ ! 0 ! 0 ! 0 ! 6 $ $ 6 3 3 6 # ! 0 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ 6 $ $ 6 3 3 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! a i c , 1 & 0 0 # 0 ( docid024244 rev 10 45/240 stm32f437xx and stm32f439xx pinouts and pin description 84 figure 12. stm32f43x wlcsp143 ballout 1. the above figure shows the package bump view. 9 % $ 7 3 ' 5 b 2 1 0 6 9 $ % & ' ( ) * + - . / 0 1 3 ( 3 & 3 & 3 ) 3 ) 3 ) 3 + 3 & 9 5 ( ) 3 $ % < 3 $ 6 6 b 5 ( * 3 ( 3 ( 3 ( 3 & 9 ' ' 3 ) 3 ) 3 + 3 & 9 6 6 $ 9 ' ' $ 3 & 3 $ 3 $ 3 % 3 % 3 * 3 * 3 ' 3 ' 3 ' 3 & 9 ' ' 3 % 3 % 3 % 3 * 3 ' 3 ' 3 ' 3 & 3 $ % 2 2 7 3 % 3 % 3 * 9 ' ' 3 ' 3 & 3 $ 9 ' ' 3 ( 3 ( 9 ' ' 3 * 3 $ 3 $ 3 $ 9 6 6 9 & $ 3 b 3 ) 3 ( 9 6 6 9 ' ' 3 * 3 * 3 & 3 & 3 $ 3 $ 3 ) 3 ) 3 ) 3 * 9 6 6 3 ' 3 & 3 & 3 $ 3 ) 3 ) 9 ' ' 3 * 3 * 3 * 3 * 3 * 9 ' ' 1 5 6 7 3 & 9 6 6 3 ' 3 ' 3 ' 9 6 6 9 6 6 3 * 3 & 3 ) 3 ) 3 * 3 ( 3 % 3 ' 3 ' 3 $ 3 $ 3 % 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 3 ( 3 % 3 ' 3 * 3 $ 3 $ 3 % 3 ( 3 ( 3 ( 3 ' 9 ' ' 3 $ 3 & 3 ) 3 ) 3 ( 3 ( 3 % 3 % 3 ' 3 & 3 % 3 ) 3 * 3 ( 3 ( 3 % 9 & $ 3 b 3 % pinouts and pin description stm32f437xx and stm32f439xx 46/240 docid024244 rev 10 figure 13. stm32f43x lqfp144 pinout 1. the above figure shows the package top view. 6 $ $ 0 $ 2 ? / . 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ' 6 $ $ 6 3 3 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 6 $ $ 6 3 3 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! 0 % 6 $ $ 0 % 6 3 3 0 % 0 % 0 ! 0 % 0 ! 6 " ! 4 0 ! 0 # 0 ! 0 # 0 ! 0 # 0 ! 0 & 0 # 0 & 0 # 0 & 0 # 0 & 0 # 0 & 6 $ $ 0 & 6 3 3 6 3 3 0 ' 6 $ $ 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 ( 0 $ 0 ( 0 $ . 2 3 4 6 $ $ 0 # 6 3 3 0 # 0 $ 0 # 0 $ 0 # 0 $ 6 3 3 ! 0 $ 6 $ $ 0 $ 6 2 % & 0 $ 6 $ $ ! 0 " 0 ! 0 " 0 ! 0 " 0 ! 0 " 0 ! 6 3 3 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 & 0 & 6 $ $ 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 6 $ $ 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ , 1 & 0 a i b 6 # ! 0 ? 6 3 3 docid024244 rev 10 47/240 stm32f437xx and stm32f439xx pinouts and pin description 84 figure 14. stm32f43x lqfp176 pinout 1. the above figure shows the package top view. - 3 6 0 $ 2 ? / . 6 $ $ 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ' 6 $ $ 6 3 3 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 6 $ $ 6 3 3 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ) 0 ) 0 % 6 $ $ 0 % 6 3 3 0 % 0 % 0 ! 0 % 0 ! 6 " ! 4 0 ! 0 ) 0 ! 0 # 0 ! 0 # 0 ! 0 & 0 # 0 & 0 # 0 & 0 # 0 & 0 # 0 & 6 $ $ 0 & 6 3 3 0 ' 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 ( 0 $ 0 ( 0 $ . 2 3 4 6 $ $ 0 # 6 3 3 0 # 0 $ 0 # 0 $ 0 # 0 $ 0 $ 0 $ 6 2 % & 0 $ 0 " 0 ! 0 " 0 ! 0 " 0 ! 0 " 0 ! " 9 0 ! 3 3 ? 2 % ' 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 & 0 & 6 3 3 6 $ $ 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 6 $ $ 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ , 1 & 0 6 # ! 0 ? 0 ) 0 ! 0 ! 6 $ $ 6 3 3 0 ) 0 ) 0 ) 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ) 0 ) 0 ( 0 ( 0 ( 6 $ $ 6 3 3 0 ( 0 # 0 ) 0 ) 0 ) 6 3 3 0 ( 0 ( 6 $ $ 6 3 3 6 $ $ 6 $ $ 6 3 3 ! 6 $ $ ! stm32f437xx and stm32f439xx pinouts and pin description docid024244 rev 10 48/240 figure 15. stm32f43x lqfp208 pinout 1. the above figure shows the package top view. - 3 6 0 ) 0 ) 0 ) 0 ) 6 $ $ 0 $ 2 ? / . 6 3 3 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ' 0 + 0 + 0 + 0 + 0 + 6 $ $ 6 3 3 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 * 0 * 0 * 0 * 0 $ 0 $ 6 $ $ 6 3 3 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! 6 $ $ 0 ) 0 % 0 ) 0 % 0 ) 0 % 0 ) 0 % 0 ( 0 % 0 ( 6 " ! 4 0 ( 0 ) 6 $ $ 0 # 6 3 3 0 # 6 # ! 0 0 # 0 ! 0 ) 0 ! 0 ) 0 ! 0 ) 0 ! 6 3 3 0 ! 6 $ $ 0 ! 0 & 0 # 0 & 0 # 0 & 0 # 0 ) 0 # 0 ) 6 $ $ 0 ) 6 3 3 0 & 0 ' 0 & 0 ' 0 & 0 ' 6 3 3 , 1 & 0 0 ' 6 $ $ 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 + 0 & 0 + 0 & 0 + 0 ( 6 3 3 0 ( 6 $ $ . 2 3 4 0 * 0 # 0 * 0 # 0 * 0 # 0 * 0 # 0 * 6 $ $ 0 * 6 3 3 ! 0 $ 6 2 % & 0 $ 6 $ $ ! 6 $ $ 0 ! 6 3 3 0 ! 0 $ 0 ! 0 $ 0 ( 0 $ 0 ( 0 $ 0 ( 0 $ 0 ( 0 $ 0 ! 0 " 6 3 3 0 " 6 $ $ 0 " 0 ! 0 ! 0 ! 0 ! 0 # 0 # 6 $ $ 6 3 3 0 " 0 " 0 " 0 ) 0 * 0 * 0 * 0 * 0 * 0 & 0 & 6 3 3 6 $ $ 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 6 $ $ 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 6 3 3 6 $ $ 0 * 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 6 $ $ 0 " docid024244 rev 10 49/240 stm32f437xx and stm32f439xx pinouts and pin description 84 figure 16. stm32f43x ufbga169 ballout 1. the above figure shows the package top view. 2. the 4 corners balls, a1,a13, n1 and n13, are not bonded internally and should be left not connected on the pcb. - 3 6 * + , " ! # $ % & ' ( - . 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # 0 # 0 # 0 ) 0 ) 6 3 3 6 $ $ 0 & 0 & 0 & 0 & 0 & 0 & 6 3 3 6 $ $ 0 & 0 ( 0 ( . 2 3 4 0 # 0 # 0 # 0 # 6 3 3 ! 6 2 % & 6 2 % & 6 $ $ ! 0 ! 0 ! 0 ! 0 ( 0 ( 0 ( 0 ( 0 ! " 9 0 ! 3 3 ? 2 % ' 6 $ $ 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 & 0 & 6 3 3 6 $ $ 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 6 $ $ 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 6 3 3 6 $ $ 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 6 $ $ 0 $ 0 $ 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 6 3 3 6 $ $ 0 # 0 # 0 # 0 # 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 6 # ! 0 ? 6 3 3 6 $ $ 0 ( 0 ( 0 ( 0 ) 0 ) 0 ) 0 ) 6 3 3 6 $ $ 0 ! 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 ' 0 ' 0 ' 6 3 3 6 $ $ 6 $ $ 0 ' 0 " 0 " 0 " 0 " 0 " " / / 4 0 " 0 " 0 % 0 % 6 3 3 0 $ 2 ? / . 0 ) 0 ) 0 ) 0 ) 6 $ $ 0 ! pinouts and pin description stm32f437xx and stm32f439xx 50/240 docid024244 rev 10 figure 17. stm32f43x ufbga176 ballout 1. the above figure shows the package top view. a i c ! 0 % 0 % 0 % 0 % 0 " 0 " 0 ' 0 ' 0 " 0 " 0 $ 0 # 0 ! 0 ! 0 ! " 0 % 0 % 0 % 0 " 0 " 0 " 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 0 # 0 # 0 ! # 6 " ! 4 0 ) 0 ) 0 ) 0 $ 2 ? / . 6 $ $ 6 $ $ 6 $ $ 6 $ $ 0 ' 0 $ 0 $ 0 ) 0 ) 0 ! $ 0 # 0 ) 0 ) 0 ) " / / 4 6 3 3 6 3 3 6 3 3 0 $ 0 $ 0 $ 0 ( 0 ) 0 ! % 0 # 0 & 0 ) 0 ) 0 ( 0 ( 0 ) 0 ! & 0 # 6 3 3 6 $ $ 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 # ! 0 0 # 0 ! ' 0 ( 6 3 3 6 $ $ 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 $ $ 0 # 0 # ( 0 ( 0 & 0 & 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 $ $ 0 ' 0 # * . 2 3 4 0 & 0 ( 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 $ $ 6 $ $ 0 ' 0 ' + 0 & 0 & 0 & 6 $ $ 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 0 ( 0 ' 0 ' 0 ' , 0 & 0 & 0 & " 9 0 ! 3 3 ? 2 % ' 0 ( 0 ( 0 $ 0 ' - 6 3 3 ! 0 # 0 & 0 # 0 # 0 # 0 " 0 ' 6 3 3 6 3 3 6 # ! 0 ? 0 ( 0 ( 0 ( 0 $ 0 $ . 6 2 % & 0 ! 0 ! 0 # 0 & 0 ' 6 $ $ 6 $ $ 6 $ $ 0 % 0 ( 0 $ 0 $ 0 $ 0 6 2 % & 0 ! 0 ! 0 ! 0 # 0 & 0 & 0 % 0 % 0 % 0 % 0 " 0 " 0 $ 0 $ 2 6 $ $ ! 0 ! 0 ! 0 " 0 " 0 & 0 & 0 % 0 % 0 % 0 % 0 " 0 " 0 " 0 " 6 3 3 0 ! docid024244 rev 10 51/240 stm32f437xx and stm32f439xx pinouts and pin description 84 figure 18. stm32f43x tfbga216 ballout 1. the above figure shows the package top view. - 3 6 ! 0 % 0 % 0 % 0 ' 0 % 0 % 0 " 0 " 0 " 0 " 0 $ 0 # 0 ! 0 ! 0 ! " 0 % 0 % 0 ' 0 " 0 " 0 " 0 ' 0 ' 0 * 0 * 0 $ 0 $ 0 # 0 # 0 ! # 6 " ! 4 0 ) 0 ) 0 + 0 + 0 + 0 ' 0 ' 0 * 0 $ 0 $ 0 $ 0 ) 0 ) 0 ! $ 0 # 0 & 0 ) 0 ) 0 ) 0 ) 0 + 0 + 0 ' 0 * 0 $ 0 $ 0 ( 0 ) 0 ! % 0 # 0 & 0 ) 0 ) 0 $ 2 ? / . " / / 4 6 $ $ 6 $ $ 6 $ $ 6 $ $ 6 # ! 0 0 ( 0 ( 0 ) 0 ! & 0 # 6 3 3 0 ) 6 $ $ 6 $ $ 6 3 3 6 3 3 6 $ $ 0 + 0 + 0 # 0 ! ' 0 ( 0 & 0 ) 0 ) 6 $ $ 6 3 3 6 $ $ 0 * 0 + 0 # 0 # ( 0 ( 0 ) 0 ( 6 $ $ 6 3 3 6 3 3 6 $ $ 0 * 0 * 0 ' 0 # * . 2 3 4 0 & 0 ( 0 ( 6 $ $ 6 3 3 6 3 3 6 $ $ 0 * 0 * 0 ' 0 ' + 0 & 0 & 0 & 0 ( 6 $ $ 6 3 3 6 3 3 6 3 3 6 3 3 6 3 3 6 $ $ 0 * 0 $ 0 " 0 $ , 0 & 0 & 0 & 0 # " 9 0 ! 3 3 2 % ' 6 3 3 6 $ $ 6 $ $ 6 $ $ 6 $ $ 6 # ! 0 0 $ 0 " 0 $ 0 $ - 6 3 3 ! 0 # 0 # 0 # 0 " 0 & 0 ' 0 & 0 * 0 $ 0 $ 0 ' 0 ' 0 * 0 ( . 6 2 % & 0 ! 0 ! 0 ! 0 # 0 & 0 ' 0 * 0 % 0 $ 0 ' 0 ' 0 ( 0 ( 0 ( 6 2 % & 0 ! 0 ! 0 ! 0 # 0 & 0 * 0 & 0 % 0 % 0 % 0 " 0 ( 0 ( 0 ( 0 ! 0 ! 0 " 0 " 0 * 0 * 0 % 0 % 0 % 0 % 0 % 0 " 0 " 0 " 6 3 3 0 & 0 2 6 $ $ ! 6 3 3 6 3 3 6 3 3 pinouts and pin description stm32f437xx and stm32f439xx 52/240 docid024244 rev 10 table 9. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tta 3.3 v tolerant i/o directly connected to adc b dedicated boot0 pin rst bidirectional reset pin with weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers table 10. stm32f437xx and stm32f439xx pin and ball definitions pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 1 1 b2 a2 1 d8 1 a3 pe2 i/o ft - traceclk, spi4_sck, sai1_mclk_a, eth_mii_txd3, fmc_a23, eventout - 2 2 c1 a1 2 c10 2 a2 pe3 i/o ft - traced0, sai1_sd_b, fmc_a19, eventout - 3 3 c2 b1 3 b11 3 a1 pe4 i/o ft - traced1, spi4_nss, sai1_fs_a, fmc_a20, dcmi_d4, lcd_b0, eventout - docid024244 rev 10 53/240 stm32f437xx and stm32f439xx pinouts and pin description 84 4 4 d1 b2 4 d9 4 b1 pe5 i/o ft - traced2, tim9_ch1, spi4_miso, sai1_sck_a, fmc_a21, dcmi_d6, lcd_g0, eventout - 5 5 d2 b3 5 e8 5 b2 pe6 i/o ft - traced3, tim9_ch2, spi4_mosi, sai1_sd_a, fmc_a22, dcmi_d7, lcd_g1, eventout - -- - - ---g6 v ss s-- - - -- - - ---f5 v dd s-- - - 66e5c16c116c1 v bat s-- - - -- nc (2) d2 7 - 7 c2 pi8 i/o ft (3) (4) eventout tamp_2 77e4d18d108d1 pc13 i/oft (3) (4) eventout tamp_1 8 8 e1 e1 9 d11 9 e1 pc14- osc32_in (pc14) i/o ft (3) (4) eventout osc32_in (5) 99f1f110e1110f1 pc15- osc32_out (pc15) i/o ft (3) (4) eventout osc32_ out (5) -- - - ---g5 v dd s-- - - - - e2 d3 11 - 11 e4 pi9 i/o ft - can1_rx, fmc_d30, lcd_vsync, eventout - - - e3 e3 12 - 12 d5 pi10 i/o ft - eth_mii_rx_er, fmc_d31, lcd_hsync, eventout - -- nc (2) e4 13 - 13 f3 pi11 i/o ft - otg_hs_ulpi_dir, eventout - - - f6 f2 14 e7 14 f2 v ss s-- - - --f4f315e1015f4 v dd s-- - - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 54/240 docid024244 rev 10 -10f2e216f1116d2 pf0 i/oft- i2c2_sda, fmc_a0, eventout - -11f3h317e917e2 pf1 i/oft- i2c2_scl, fmc_a1, eventout - - 12 g5 h2 18 f10 18 g2 pf2 i/o ft - i2c2_smba, fmc_a2, eventout - - - - - - - 19 e3 pi12 i/o ft - lcd_hsync, eventout - - - - - - - 20 g3 pi13 i/o ft - lcd_vsync, eventout - - - - - - - 21 h3 pi14 i/o ft lcd_clk, eventout - -13g4j219g1122h2 pf3 i/oft (5) fmc_a3, eventout adc3_in9 -14g3j320f923j2 pf4 i/oft (5) fmc_a4, eventout adc3_ in14 -15h3k321f824k3 pf5 i/oft (5) fmc_a5, eventout adc3_ in15 10 16 g7 g2 22 h7 25 h6 v ss s-- - - 11 17 g8 g3 23 - 26 h5 v dd s-- - - -18 nc (2) k2 24 g10 27 k2 pf6 i/o ft (5) tim10_ch1, spi5_nss, sai1_sd_b, uart7_rx, fmc_niord, eventout adc3_in4 -19 nc (2) k1 25 f7 28 k1 pf7 i/o ft (5) tim11_ch1, spi5_sck, sai1_mclk_b, uart7_tx, fmc_nreg, eventout adc3_in5 -20 nc (2) l3 26 h11 29 l3 pf8 i/o ft (5) spi5_miso, sai1_sck_b, tim13_ch1, fmc_niowr, eventout adc3_in6 table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 55/240 stm32f437xx and stm32f439xx pinouts and pin description 84 -21 nc (2) l2 27 g8 30 l2 pf9 i/o ft (5) spi5_mosi, sai1_fs_b, tim14_ch1, fmc_cd, eventout adc3_in7 -22h1l128g931l1 pf10 i/oft (5) fmc_intr, dcmi_d11, lcd_de, eventout adc3_in8 12 23 g2 g1 29 j11 32 g1 ph0-osc_in (ph0) i/o ft - eventout osc_in (5) 13 24 g1 h1 30 h10 33 h1 ph1- osc_out (ph1) i/o ft - eventout osc_out (5) 14 25 h2 j1 31 h9 34 j1 nrst i/o rs t -- - 15 26 g6 m2 32 h8 35 m2 pc0 i/o ft (5) otg_hs_ulpi_stp, fmc_sdnwe, eventout adc123_ in10 16 27 h5 m3 33 k11 36 m3 pc1 i/o ft (5) eth_mdc, eventout adc123_ in11 17 28 h6 m4 34 j10 37 m4 pc2 i/o ft (5) spi2_miso, i2s2ext_sd, otg_hs_ulpi_dir, eth_mii_txd2, fmc_sdne0, eventout adc123_ in12 18 29 h7 m5 35 j9 38 l4 pc3 i/o ft (5) spi2_mosi/i2s2_sd, otg_hs_ulpi_nxt, eth_mii_tx_clk, fmc_sdcke0, eventout adc123_ in13 19 30 - - 36 g7 39 j5 v dd s-- - - -- - - ---j6 v ss s-- - - 20 31 j1 m1 37 k10 40 m1 v ssa s-- - - --j2n1---n1 v ref ? s-- - - 21 32 j3 p1 38 l11 41 p1 v ref+ s-- - - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 56/240 docid024244 rev 10 22 33 j4 r1 39 l10 42 r1 v dda s-- - - 23 34 j5 n3 40 k9 43 n3 pa0-wkup (pa0) i/o ft (6) tim2_ch1/tim2_etr, tim5_ch1, tim8_etr, usart2_cts, uart4_tx, eth_mii_crs, eventout adc123_ in0/wkup (5) 24 35 k1 n2 41 k8 44 n2 pa1 i/o ft (5) tim2_ch2, tim5_ch2, usart2_rts, uart4_rx, eth_mii_rx_clk/eth _rmii_ref_clk, eventout adc123_ in1 25 36 k2 p2 42 l9 45 p2 pa2 i/o ft (5) tim2_ch3, tim5_ch3, tim9_ch1, usart2_tx, eth_mdio, eventout adc123_ in2 - - l2 f4 43 - 46 k4 ph2 i/o ft - eth_mii_crs, fmc_sdcke0, lcd_r0, eventout - - - l1 g4 44 - 47 j4 ph3 i/o ft - eth_mii_col, fmc_sdne0, lcd_r1, eventout - - - m2 h4 45 - 48 h4 ph4 i/o ft - i2c2_scl, otg_hs_ulpi_nxt, eventout - - - l3 j4 46 - 49 j3 ph5 i/o ft - i2c2_sda, spi5_nss, fmc_sdnwe, eventout - 26 37 k3 r2 47 m11 50 r2 pa3 i/o ft (5) tim2_ch4, tim5_ch4, tim9_ch2, usart2_rx, otg_hs_ulpi_d0, eth_mii_col, lcd_b5, eventout adc123_ in3 27 38 - - - 51 k6 v ss s-- - - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 57/240 stm32f437xx and stm32f439xx pinouts and pin description 84 - - m1 l4 48 n11 - l5 bypass_ reg ift- - - 28 39 j11 k4 49 j8 52 k5 v dd s-- - - 29 40 n2 n4 50 m10 53 n4 pa4 i/o tta (5) spi1_nss, spi3_nss/i2s3_ws, usart2_ck, otg_hs_sof, dcmi_hsync, lcd_vsync, eventout adc12_ in4 /dac_ out1 30 41 m3 p4 51 m9 54 p4 pa5 i/o tta (5) tim2_ch1/tim2_etr, tim8_ch1n, spi1_sck, otg_hs_ulpi_ck, eventout adc12_ in5/dac_ out2 31 42 n3 p3 52 n10 55 p3 pa6 i/o ft (5) tim1_bkin, tim3_ch1, tim8_bkin, spi1_miso, tim13_ch1, dcmi_pixclk, lcd_g2, eventout adc12_ in6 32 43 k4 r3 53 l8 56 r3 pa7 i/o ft (5) tim1_ch1n, tim3_ch2, tim8_ch1n, spi1_mosi, tim14_ch1, eth_mii_rx_dv/eth_ rmii_crs_dv, eventout adc12_ in7 33 44 l4 n5 54 m8 57 n5 pc4 i/o ft (5) eth_mii_rxd0/eth_ rmii_rxd0, eventout adc12_ in14 34 45 m4 p5 55 n9 58 p5 pc5 i/o ft (5) eth_mii_rxd1/eth_ rmii_rxd1, eventout adc12_ in15 -- - - -j759l7 v dd s-- - - - - - - - - 60 l6 vss s - - - - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 58/240 docid024244 rev 10 35 46 n4 r5 56 n8 61 r5 pb0 i/o ft (5) tim1_ch2n, tim3_ch3, tim8_ch2n, lcd_r3, otg_hs_ulpi_d1, eth_mii_rxd2, eventout adc12_ in8 36 47 k5 r4 57 k7 62 r4 pb1 i/o ft (5) tim1_ch3n, tim3_ch4, tim8_ch3n, lcd_r6, otg_hs_ulpi_d2, eth_mii_rxd3, eventout adc12_ in9 37 48 l5 m6 58 l7 63 m5 pb2-boot1 (pb2) i/o ft - eventout - - - - - - - 64 g4 pi15 i/o ft - lcd_r0, eventout - - - - - - - 65 r6 pj0 i/o ft - lcd_r1, eventout - - - - - - - 66 r7 pj1 i/o ft - lcd_r2, eventout - - - - - - - 67 p7 pj2 i/o ft - lcd_r3, eventout - - - - - - - 68 n8 pj3 i/o ft - lcd_r4, eventout - - - - - - - 69 m9 pj4 i/o ft - lcd_r5, eventout - - 49 m5 r6 59 m7 70 p8 pf11 i/o ft - spi5_mosi, fmc_sdnras, dcmi_d12, eventout - - 50 n5 p6 60 n7 71 m6 pf12 i/o ft - fmc_a6, eventout - - 51g9m861 - 72k7 v ss s- - - - 52 d10 n8 62 - 73 l8 v dd s- - - - 53 m6 n6 63 k6 74 n6 pf13 i/o ft - fmc_a7, eventout - - 54 k7 r7 64 l6 75 p6 pf14 i/o ft - fmc_a8, eventout - - 55 l7 p7 65 m6 76 m8 pf15 i/o ft - fmc_a9, eventout - - 56 n6 n7 66 n6 77 n7 pg0 i/o ft - fmc_a10, eventout - - 57 m7 m7 67 k5 78 m7 pg1 i/o ft - fmc_a11, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 59/240 stm32f437xx and stm32f439xx pinouts and pin description 84 38 58 n7 r8 68 l5 79 r8 pe7 i/o ft - tim1_etr, uart7_rx, fmc_d4, eventout - 39 59 j8 p8 69 m5 80 n9 pe8 i/o ft - tim1_ch1n, uart7_tx, fmc_d5, eventout - 40 60 k8 p9 70 n5 81 p9 pe9 i/o ft - tim1_ch1, fmc_d6, eventout - -61j6m971h382k8 v ss s- - - 62 g10 n9 72 j5 83 l9 v dd s- - 41 63 l8 r9 73 j4 84 r9 pe10 i/o ft - tim1_ch2n, fmc_d7, eventout - 42 64 m8 p10 74 k4 85 p10 pe11 i/o ft - tim1_ch2, spi4_nss, fmc_d8, lcd_g3, eventout - 43 65 n8 r10 75 l4 86 r10 pe12 i/o ft - tim1_ch3n, spi4_sck, fmc_d9, lcd_b4, eventout - 44 66 h9 n11 76 n4 87 r12 pe13 i/o ft - tim1_ch3, spi4_miso, fmc_d10, lcd_de, eventout - 45 67 j9 p11 77 m4 88 p11 pe14 i/o ft - tim1_ch4, spi4_mosi, fmc_d11, lcd_clk, eventout - 46 68 k9 r11 78 l3 89 r11 pe15 i/o ft - tim1_bkin, fmc_d12, lcd_r7, eventout - 47 69 l9 r12 79 m3 90 p12 pb10 i/o ft - tim2_ch3, i2c2_scl, spi2_sck/i2s2_ck, usart3_tx, otg_hs_ulpi_d3, eth_mii_rx_er, lcd_g4, eventout - 48 70 m9 r13 80 n3 91 r13 pb11 i/o ft - tim2_ch4, i2c2_sda, usart3_rx, otg_hs_ulpi_d4, eth_mii_tx_en/eth_ rmii_tx_en, lcd_g5, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 60/240 docid024244 rev 10 49 71 n9 m10 81 n2 92 l11 v cap_1 s-- - - -- - - -h293k9 v ss s-- - - 50 72 f8 n10 82 j6 94 l10 v dd s-- - - - - - - - - 95 m14 pj5 i/o - - lcd_r6, eventout - - - n10 m11 83 - 96 p13 ph6 i/o ft - i2c2_smba, spi5_sck, tim12_ch1, eth_mii_rxd2, fmc_sdne1, dcmi_d8, eventout - - - m10 n12 84 - 97 n13 ph7 i/o ft - i2c3_scl, spi5_miso, eth_mii_rxd3, fmc_sdcke1, dcmi_d9, eventout - - - l10 m12 85 - 98 p14 ph8 i/o ft - i2c3_sda, fmc_d16, dcmi_hsync, lcd_r2, eventout - - - k10 m13 86 - 99 n14 ph9 i/o ft - i2c3_smba, tim12_ch2, fmc_d17, dcmi_d0, lcd_r3, eventout - - - n11 l13 87 - 100 p15 ph10 i/o ft - tim5_ch1, fmc_d18, dcmi_d1, lcd_r4, eventout - - - m11 l12 88 - 101 n15 ph11 i/o ft - tim5_ch2, fmc_d19, dcmi_d2, lcd_r5, eventout - - - l11 k12 89 - 102 m15 ph12 i/o ft - tim5_ch3, fmc_d20, dcmi_d3, lcd_r6, eventout - --e7h1290--k10 v ss s-- - - - - h8 j12 91 - 103 k11 v dd s-- - - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 61/240 stm32f437xx and stm32f439xx pinouts and pin description 84 51 73 n12 p12 92 m2 104 l13 pb12 i/o ft - tim1_bkin, i2c2_smba, spi2_nss/i2s2_ws, usart3_ck, can2_rx, otg_hs_ulpi_d5, eth_mii_txd0/eth_r mii_txd0, otg_hs_id, eventout - 52 74 m12 p13 93 n1 105 k14 pb13 i/o ft - tim1_ch1n, spi2_sck/i2s2_ck, usart3_cts, can2_tx, otg_hs_ulpi_d6, eth_mii_txd1/eth_r mii_txd1, eventout otg_hs_ vbus 53 75 m13 r14 94 k3 106 r14 pb14 i/o ft - tim1_ch2n, tim8_ch2n, spi2_miso, i2s2ext_sd, usart3_rts, tim12_ch1, otg_hs_dm, eventout - 54 76 l13 r15 95 j3 107 r15 pb15 i/o ft - rtc_refin, tim1_ch3n, tim8_ch3n, spi2_mosi/i2s2_sd, tim12_ch2, otg_hs_dp, eventout - 55 77 l12 p15 96 l2 108 l15 pd8 i/o ft - usart3_tx, fmc_d13, eventout - 56 78 k13 p14 97 m1 109 l14 pd9 i/o ft - usart3_rx, fmc_d14, eventout - 57 79 k11 n15 98 h4 110 k15 pd10 i/o ft - usart3_ck, fmc_d15, lcd_b3, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 62/240 docid024244 rev 10 58 80 h10 n14 99 k2 111 n10 pd11 i/o ft - usart3_cts, fmc_a16, eventout - 59 81 j13 n13 100 h6 112 m10 pd12 i/o ft - tim4_ch1, usart3_rts, fmc_a17, eventout - 60 82 k12 m15 101 h5 113 m11 pd13 i/o ft - tim4_ch2, fmc_a18, eventout - -83 - -102-114j10 v ss s- - - - 84 f7 j13 103 l1 115 j11 v dd s- - - 61 85 h11 m14 104 j2 116 l12 pd14 i/o ft - tim4_ch3, fmc_d0, eventout - 62 86 j12 l14 105 k1 117 k13 pd15 i/o ft - tim4_ch4, fmc_d1, eventout - - - - - - - 118 k12 pj6 i/o ft - lcd_r7, eventout - - - - - - - 119 j12 pj7 i/o ft - lcd_g0, eventout - - - - - - - 120 h12 pj8 i/o ft - lcd_g1, eventout - - - - - - - 121 j13 pj9 i/o ft - lcd_g2, eventout - - - - - - - 122 h13 pj10 i/o ft - lcd_g3, eventout - - - - - - - 123 g12 pj11 i/o ft - lcd_g4, eventout - -- - - --124h11 vdd i/oft- - - - - - - - - 125 h10 vss i/o ft - - - - - - - - - 126 g13 pk0 i/o ft - lcd_g5, eventout - - - - - - - 127 f12 pk1 i/o ft - lcd_g6, eventout - - - - - - - 128 f13 pk2 i/o ft - lcd_g7, eventout - - 87 h13 l15 106 j1 129 m13 pg2 i/o ft - fmc_a12, eventout - -88 nc (2) k15 107 g3 130 m12 pg3 i/o ft - fmc_a13, eventout - - 89 h12 k14 108 g5 131 n12 pg4 i/o ft - fmc_a14/fmc_ba0, eventout - - 90 g13 k13 109 g6 132 n11 pg5 i/o ft - fmc_a15/fmc_ba1, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 63/240 stm32f437xx and stm32f439xx pinouts and pin description 84 - 91 g11 j15 110 g4 133 j15 pg6 i/o ft - fmc_int2, dcmi_d12, lcd_r7, eventout - - 92 g12 j14 111 h1 134 j14 pg7 i/o ft - usart6_ck, fmc_int3, dcmi_d13, lcd_clk, eventout - - 93 f13 h14 112 g2 135 h14 pg8 i/o ft - spi6_nss, usart6_rts, eth_pps_out, fmc_sdclk, eventout - -94j7g12113d2136g10 v ss s- - - -95e6h13114g1137g11 v dd s- - - 63 96 f9 h15 115 f2 138 h15 pc6 i/o ft - tim3_ch1, tim8_ch1, i2s2_mck, usart6_tx, sdio_d6, dcmi_d0, lcd_hsync, eventout - 64 97 f10 g15 116 f3 139 g15 pc7 i/o ft - tim3_ch2, tim8_ch2, i2s3_mck, usart6_rx, sdio_d7, dcmi_d1, lcd_g6, eventout - 65 98 f11 g14 117 e4 140 g14 pc8 i/o ft - tim3_ch3, tim8_ch3, usart6_ck, sdio_d0, dcmi_d2, eventout - 66 99 f12 f14 118 e3 141 f14 pc9 i/o ft - mco2, tim3_ch4, tim8_ch4, i2c3_sda, i2s_ckin, sdio_d1, dcmi_d3, eventout - 67 100 e13 f15 119 f1 142 f15 pa8 i/o ft - mco1, tim1_ch1, i2c3_scl, usart1_ck, otg_fs_sof, lcd_r6, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 64/240 docid024244 rev 10 68 101 e8 e15 120 e2 143 e15 pa9 i/o ft - tim1_ch2, i2c3_smba, usart1_tx, dcmi_d0, eventout otg_fs_ vbus 69 102 e9 d15 121 d5 144 d15 pa10 i/o ft - tim1_ch3, usart1_rx, otg_fs_id, dcmi_d1, eventout - 70 103 e10 c15 122 d4 145 c15 pa11 i/o ft - tim1_ch4, usart1_cts, can1_rx, lcd_r4, otg_fs_dm, eventout - 71 104 e11 b15 123 e1 146 b15 pa12 i/o ft - tim1_etr, usart1_rts, can1_tx, lcd_r5, otg_fs_dp, eventout - 72 105 e12 a15 124 d3 147 a15 pa13 (jtms- swdio) i/o ft - jtms-swdio, eventout - 73 106 d12 f13 125 d1 148 e11 v cap_2 s- - - 74 107 j10 f12 126 d2 149 f10 v ss s- - - 75 108 h4 g13 127 c1 150 f11 v dd s- - - - - d13 e12 128 - 151 e12 ph13 i/o ft - tim8_ch1n, can1_tx, fmc_d21, lcd_g2, eventout - - - c13 e13 129 - 152 e13 ph14 i/o ft - tim8_ch2n, fmc_d22, dcmi_d4, lcd_g3, eventout - - - c12 d13 130 - 153 d13 ph15 i/o ft - tim8_ch3n, fmc_d23, dcmi_d11, lcd_g4, eventout - - - b13 e14 131 - 154 e14 pi0 i/o ft - tim5_ch4, spi2_nss/i2s2_ws (7) , fmc_d24, dcmi_d13, lcd_g5, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 65/240 stm32f437xx and stm32f439xx pinouts and pin description 84 - - c11 d14 132 - 155 d14 pi1 i/o ft - spi2_sck/i2s2_ck (7) , fmc_d25, dcmi_d8, lcd_g6, eventout - - - b12 c14 133 - 156 c14 pi2 i/o ft - tim8_ch4, spi2_miso, i2s2ext_sd, fmc_d26, dcmi_d9, lcd_g7, eventout - - - a12 c13 134 - 157 c13 pi3 i/o ft - tim8_etr, spi2_mosi/i2s2_sd, fmc_d27, dcmi_d10, eventout - --d11d9135f5-f9 v ss s- - - - - d3 c9 136 a1 158 e10 v dd s- - - 76 109 a11 a14 137 b1 159 a14 pa14 (jtck- swclk) i/o ft - jtck-swclk/ eventout - 77 110 b11 a13 138 c2 160 a13 pa15 (jtdi) i/o ft - jtdi, tim2_ch1/tim2_etr, spi1_nss, spi3_nss/i2s3_ws, eventout - 78 111 c10 b14 139 a2 161 b14 pc10 i/o ft - spi3_sck/i2s3_ck, usart3_tx, uart4_tx, sdio_d2, dcmi_d8, lcd_r2, eventout - 79 112 b10 b13 140 b2 162 b13 pc11 i/o ft - i2s3ext_sd, spi3_miso, usart3_rx, uart4_rx, sdio_d3, dcmi_d4, eventout - 80 113 a10 a12 141 c3 163 a12 pc12 i/o ft - spi3_mosi/i2s3_sd, usart3_ck, uart5_tx, sdio_ck, dcmi_d9, eventout - 81 114 d9 b12 142 b3 164 b12 pd0 i/o ft - can1_rx, fmc_d2, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 66/240 docid024244 rev 10 82 115 c9 c12 143 c4 165 c12 pd1 i/o ft - can1_tx, fmc_d3, eventout - 83 116 b9 d12 144 a3 166 d12 pd2 i/o ft - tim3_etr, uart5_rx, sdio_cmd, dcmi_d11, eventout - 84 117 a9 d11 145 b4 167 c11 pd3 i/o ft - spi2_sck/i2s2_ck, usart2_cts, fmc_clk, dcmi_d5, lcd_g7, eventout - 85 118 d8 d10 146 b5 168 d11 pd4 i/o ft - usart2_rts, fmc_noe, eventout - 86 119 c8 c11 147 a4 169 c10 pd5 i/o ft - usart2_tx, fmc_nwe, eventout - - 120 - d8 148 - 170 f8 v ss s- - - - 121 d6 c8 149 c5 171 e9 v dd s- - - 87 122 b8 b11 150 f4 172 b11 pd6 i/o ft - spi3_mosi/i2s3_sd, sai1_sd_a, usart2_rx, fmc_nwait, dcmi_d10, lcd_b2, eventout - 88 123 a8 a11 151 a5 173 a11 pd7 i/o ft - usart2_ck, fmc_ne1/fmc_nce2, eventout - - - - - - - 174 b10 pj12 i/o ft - lcd_b0, eventout - - - - - - - 175 b9 pj13 i/o ft - lcd_b1, eventout - - - - - - - 176 c9 pj14 i/o ft - lcd_b2, eventout - - - - - - - 177 d10 pj15 i/o ft - lcd_b3, eventout - -124 nc (2) c10 152 e5 178 d9 pg9 i/o ft - usart6_rx, fmc_ne2/fmc_nce3, dcmi_vsync (8) , eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 67/240 stm32f437xx and stm32f439xx pinouts and pin description 84 - 125 c7 b10 153 c6 179 c8 pg10 i/o ft - lcd_g3, fmc_nce4_1/fmc_n e3, dcmi_d2, lcd_b2, eventout - - 126 b7 b9 154 b6 180 b8 pg11 i/o ft - eth_mii_tx_en/eth_ rmii_tx_en, fmc_nce4_2, dcmi_d3, lcd_b3, eventout - - 127 a7 b8 155 a6 181 c7 pg12 i/o ft - spi6_miso, usart6_rts, lcd_b4, fmc_ne4, lcd_b1, eventout - -128 nc (2) a8 156 d6 182 b3 pg13 i/o ft - spi6_sck, usart6_cts, eth_mii_txd0/eth_r mii_txd0, fmc_a24, eventout - -129 nc (2) a7 157 f6 183 a4 pg14 i/o ft - spi6_mosi, usart6_tx, eth_mii_txd1/eth_r mii_txd1, fmc_a25, eventout - - 130 d7 d7 158 - 184 f7 v ss s- - - - 131 l6 c7 159 e6 185 e8 v dd s- - - - - - - - - 186 d8 pk3 i/o ft - lcd_b4, eventout - - - - - - - 187 d7 pk4 i/o ft - lcd_b5, eventout - - - - - - - 188 c6 pk5 i/o ft - lcd_b6, eventout - - - - - - - 189 c5 pk6 i/o ft - lcd_b7, eventout - - - - - - - 190 c4 pk7 i/o ft - lcd_de, eventout - - 132 c6 b7 160 a7 191 b7 pg15 i/o ft - usart6_cts, fmc_sdncas, dcmi_d13, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 68/240 docid024244 rev 10 89 133 b6 a10 161 b7 192 a10 pb3 (jtdo/trace swo) i/o ft - jtdo/traceswo, tim2_ch2, spi1_sck, spi3_sck/i2s3_ck, eventout - 90 134 a6 a9 162 c7 193 a9 pb4 (njtrst) i/o ft - njtrst, tim3_ch1, spi1_miso, spi3_miso, i2s3ext_sd, eventout - 91 135 d5 a6 163 c8 194 a8 pb5 i/o ft - tim3_ch2, i2c1_smba, spi1_mosi, spi3_mosi/i2s3_sd, can2_rx, otg_hs_ulpi_d7, eth_pps_out, fmc_sdcke1, dcmi_d10, eventout - 92 136 c5 b6 164 a8 195 b6 pb6 i/o ft - tim4_ch1, i2c1_scl, usart1_tx, can2_tx, fmc_sdne1, dcmi_d5, eventout - 93 137 b5 b5 165 b8 196 b5 pb7 i/o ft - tim4_ch2, i2c1_sda, usart1_rx, fmc_nl, dcmi_vsync, eventout - 94 138 a5 d6 166 c9 197 e6 boot0 i b - v pp 95 139 d4 a5 167 a9 198 a7 pb8 i/o ft - tim4_ch3, tim10_ch1, i2c1_scl, can1_rx, eth_mii_txd3, sdio_d4, dcmi_d6, lcd_b6, eventout - table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 docid024244 rev 10 69/240 stm32f437xx and stm32f439xx pinouts and pin description 84 96 140 c4 b4 168 b9 199 b4 pb9 i/o ft - tim4_ch4, tim11_ch1, i2c1_sda, spi2_nss/i2s2_ws, can1_tx, sdio_d5, dcmi_d7, lcd_b7, eventout - 97 141 b4 a4 169 b10 200 a6 pe0 i/o ft - tim4_etr, uart8_rx, fmc_nbl0, dcmi_d2, eventout - 98 142 a4 a3 170 a10 201 a5 pe1 i/o ft - uart8_tx, fmc_nbl1, dcmi_d3, eventout - 99 - f5 d5 - - 202 f6 v ss s- - - 143 c3 c6 171 a11 203 e5 pdr_on s - - 100 144 k6 c5 172 d7 204 e7 v dd s- - - - b3 d4 173 - 205 c3 pi4 i/o ft - tim8_bkin, fmc_nbl2, dcmi_d5, lcd_b4, eventout - - - a3 c4 174 - 206 d3 pi5 i/o ft - tim8_ch1, fmc_nbl3, dcmi_vsync, lcd_b5, eventout - - - a2 c3 175 - 207 d6 pi6 i/o ft - tim8_ch2, fmc_d28, dcmi_d6, lcd_b6, eventout - - - b1 c2 176 - 208 d4 pi7 i/o ft - tim8_ch3, fmc_d29, dcmi_d7, lcd_b7, eventout - 1. function availability depends on the chosen device. 2. nc (not-connected) pins are not bonded. they must be configur ed by software to output push-pull and forced to 0 in the output data register to avoid extra cu rrent consumption in low power modes. 3. pc13, pc14, pc15 and pi8 are supplied through the power switch . since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a current source (e.g. to drive an led). table 10. stm32f437xx and stm32f439xx pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions additional functions lqfp100 lqfp144 ufbga169 ufbga176 lqfp176 wlcsp143 lqfp208 tfbga216 pinouts and pin description stm32f437xx and stm32f439xx 70/240 docid024244 rev 10 4. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main reset) . for details on how to manage these i/os, refer to the rtc register description sections in the stm32f4xx reference manual, available fr om the stmicroelectronics website: www.st.com . 5. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). 6. if the device is delivered in an wlcsp143, ufbg a169, ufbga176, lqfp176 or tfbga216 package, and the bypass_reg pin is set to v dd (regulator off/internal reset on mode), then pa 0 is used as an internal reset (active low). 7. pi0 and pi1 cannot be used for i2s2 full-duplex mode. 8. the dcmi_vsync alternate function on pg9 is only available on silicon revision 3. docid024244 rev 10 71/240 stm32f437xx and stm32f439xx pinouts and pin description 84 table 11. fmc pin definition pin name cf nor/psram/ sram nor/psram mux nand16 sdram pf0 a0 a0 a0 pf1 a1 a1 a1 pf2 a2 a2 a2 pf3 a3 a3 a3 pf4 a4 a4 a4 pf5 a5 a5 a5 pf12 a6 a6 a6 pf13 a7 a7 a7 pf14 a8 a8 a8 pf15 a9 a9 a9 pg0 a10 a10 a10 pg1 a11 a11 pg2 a12 a12 pg3 a13 pg4 a14 ba0 pg5 a15 ba1 pd11 a16 a16 cle pd12 a17 a17 ale pd13 a18 a18 pe3 a19 a19 pe4 a20 a20 pe5 a21 a21 pe6 a22 a22 pe2 a23 a23 pg13 a24 a24 pg14 a25 a25 pd14 d0 d0 da0 d0 d0 pd15 d1 d1 da1 d1 d1 pd0d2 d2da2d2 d2 pd1d3 d3da3d3 d3 pe7 d4 d4 da4 d4 d4 pe8 d5 d5 da5 d5 d5 pe9 d6 d6 da6 d6 d6 pe10 d7 d7 da7 d7 d7 pinouts and pin description stm32f437xx and stm32f439xx 72/240 docid024244 rev 10 pe11 d8 d8 da8 d8 d8 pe12 d9 d9 da9 d9 d9 pe13 d10 d10 da10 d10 d10 pe14 d11 d11 da11 d11 d11 pe15 d12 d12 da12 d12 d12 pd8 d13 d13 da13 d13 d13 pd9 d14 d14 da14 d14 d14 pd10 d15 d15 da15 d15 d15 ph8 d16 d16 ph9 d17 d17 ph10 d18 d18 ph11 d19 d19 ph12 d20 d20 ph13 d21 d21 ph14 d22 d22 ph15 d23 d23 pi0 d24 d24 pi1 d25 d25 pi2 d26 d26 pi3 d27 d27 pi6 d28 d28 pi7 d29 d29 pi9 d30 d30 pi10 d31 d31 pd7 ne1 ne1 nce2 pg9 ne2 ne2 nce3 pg10 nce4_1 ne3 ne3 pg11 nce4_2 pg12 ne4 ne4 pd3 clk clk pd4 noe noe noe noe pd5 nwe nwe nwe nwe pd6 nwait nwait nwait nwait pb7 nl(nadv) nl(nadv) table 11. fmc pin definition (continued) pin name cf nor/psram/ sram nor/psram mux nand16 sdram docid024244 rev 10 73/240 stm32f437xx and stm32f439xx pinouts and pin description 84 pf6 niord pf7 nreg pf8 niowr pf9 cd pf10 intr pg6 int2 pg7 int3 pe0 nbl0 nbl0 nbl0 pe1 nbl1 nbl1 nbl1 pi4 nbl2 nbl2 pi5 nbl3 nbl3 pg8 sdclk pc0 sdnwe pf11 sdnras pg15 sdncas ph2 sdcke0 ph3 sdne0 ph6 sdne1 ph7 sdcke1 ph5 sdnwe pc2 sdne0 pc3 sdcke0 pb5 sdcke1 pb6 sdne1 table 11. fmc pin definition (continued) pin name cf nor/psram/ sram nor/psram mux nand16 sdram stm32f437xx and stm32f439xx pinouts and pin description docid024244 rev 10 74/240 table 12. stm32f437xx and stm32f439xx alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys port a pa0 - tim2_ ch1/tim2 _etr tim5_ ch1 tim8_ etr -- - usart2_ cts uart4_tx - - eth_mii_ crs --- even tout pa1 - tim2_ ch2 tim5_ ch2 --- - usart2_ rts uart4_rx - - eth_mii_ rx_clk/e th_rmii_ ref_clk --- even tout pa2 - tim2_ ch3 tim5_ ch3 tim9_ ch1 -- - usart2_ tx --- eth_ mdio --- even tout pa3 - tim2_ ch4 tim5_ ch4 tim9_ ch2 -- - usart2_ rx -- otg_hs_ ulpi_d0 eth_mii_ col - - lcd_b5 even tout pa4 - - - - - spi1_ nss spi3_ nss/ i2s3_ws usart2_ ck ---- otg_hs_ sof dcmi_ hsync lcd_ vsync even tout pa5 - tim2_ ch1/tim2 _etr - tim8_ ch1n - spi1_ sck -- - - otg_hs_ ulpi_ck ---- even tout pa6 - tim1_ bkin tim3_ ch1 tim8_ bkin - spi1_ miso - - - tim13_ch1 - - - dcmi_ pixclk lcd_g2 even tout pa7 - tim1_ ch1n tim3_ ch2 tim8_ ch1n - spi1_ mosi - - - tim14_ch1 - eth_mii_ rx_dv/ eth_rmii _crs_dv --- even tout pa8 mco1 tim1_ ch1 -- i2c3_ scl -- usart1_ ck -- otg_fs_ sof - - - lcd_r6 even tout pa9 - tim1_ ch2 -- i2c3_ smba -- usart1_ tx ----- dcmi_ d0 - even tout pa10 - tim1_ ch3 ----- usart1_ rx -- otg_fs_ id -- dcmi_ d1 - even tout pa11 - tim1_ ch4 ----- usart1_ cts - can1_rx otg_fs_ dm - - - lcd_r4 even tout pa12 - tim1_ etr ----- usart1_ rts -can1_tx otg_fs_ dp - - - lcd_r5 even tout pinouts and pin description stm32f437xx and stm32f439xx 75/240 docid024244 rev 10 port a pa13 jtms- swdi o ------- - - - - --- even tout pa14 jtck- swcl k ------- - - - - --- even tout pa15 jtdi tim2_ ch1/tim2 _etr --- spi1_ nss spi3_ nss/ i2s3_ws -- - -- --- even tout port b pb0 - tim1_ ch2n tim3_ ch3 tim8_ ch2n - - - - - lcd_r3 otg_hs_ ulpi_d1 eth_mii_ rxd2 --- even tout pb1 - tim1_ ch3n tim3_ ch4 tim8_ ch3n - - - - - lcd_r6 otg_hs_ ulpi_d2 eth_mii_ rxd3 --- even tout pb2 - - - - - - - - - - - - - - - even tout pb3 jtdo/ trac eswo tim2_ ch2 --- spi1_ sck spi3_ sck/ i2s3_ck -- - -- --- even tout pb4 njtr st - tim3_ ch1 -- spi1_ miso spi3_ miso i2s3ext_ sd ------- even tout pb5 - - tim3_ ch2 - i2c1_ smba spi1_ mosi spi3_ mosi/ i2s3_sd - - can2_rx otg_hs_ ulpi_d7 eth_pps _out fmc_ sdcke1 dcmi_ d10 - even tout pb6 - - tim4_ ch1 - i2c1_ scl -- usart1_ tx -can2_tx- - fmc_ sdne1 dcmi_ d5 - even tout pb7 - - tim4_ ch2 - i2c1_ sda -- usart1_ rx - - - - fmc_nl dcmi_ vsync - even tout pb8 - - tim4_ ch3 tim10_ ch1 i2c1_ scl - - - - can1_rx - eth_mii_ txd3 sdio_d4 dcmi_ d6 lcd_b6 even tout pb9 - - tim4_ ch4 tim11_ ch1 i2c1_ sda spi2_ nss/i2 s2_ws - - - can1_tx - - sdio_d5 dcmi_ d7 lcd_b7 even tout pb10 - tim2_ ch3 -- i2c2_ scl spi2_ sck/i2 s2_ck - usart3_ tx -- otg_hs_ ulpi_d3 eth_mii_ rx_er - - lcd_g4 even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys stm32f437xx and stm32f439xx pinouts and pin description docid024244 rev 10 76/240 port b pb11 - tim2_ ch4 -- i2c2_ sda -- usart3_ rx -- otg_hs_ ulpi_d4 eth_mii_ tx_en/ eth_rmii _tx_en - - lcd_g5 even tout pb12 - tim1_ bkin -- i2c2_ smba spi2_ nss/i2 s2_ws - usart3_ ck - can2_rx otg_hs_ ulpi_d5 eth_mii_ txd0/eth _rmii_ txd0 otg_hs_ id -- even tout pb13 - tim1_ ch1n --- spi2_ sck/i2 s2_ck - usart3_ cts -can2_tx otg_hs_ ulpi_d6 eth_mii_ txd1/eth _rmii_tx d1 --- even tout pb14 - tim1_ ch2n - tim8_ ch2n - spi2_ miso i2s2ext_ sd usart3_ rts - tim12_ch1 - - otg_hs_ dm -- even tout pb15 rtc_ refin tim1_ ch3n - tim8_ ch3n - spi2_ mosi/i2 s2_sd - - - tim12_ch2 - - otg_hs_ dp -- even tout port c pc0 - - - - - - - - - - otg_hs_ ulpi_stp - fmc_sdn we -- even tout pc1 - - - - - - - - - - - eth_mdc - - - even tout pc2 - - - - - spi2_ miso i2s2ext_ sd -- - otg_hs_ ulpi_dir eth_mii_ txd2 fmc_ sdne0 -- even tout pc3 - - - - - spi2_ mosi/i2 s2_sd -- - - otg_hs_ ulpi_nxt eth_mii_ tx_clk fmc_ sdcke0 -- even tout pc4 - - - - - - - - - - - eth_mii_ rxd0/eth _rmii_ rxd0 --- even tout pc5 - - - - - - - - - - - eth_mii_ rxd1/eth _rmii_ rxd1 --- even tout pc6 - - tim3_ ch1 tim8_ ch1 - i2s2_ mck -- usart6_ tx - - - sdio_d6 dcmi_ d0 lcd_ hsync even tout pc7 - - tim3_ ch2 tim8_ ch2 -- i2s3_ mck - usart6_ rx - - - sdio_d7 dcmi_ d1 lcd_g6 even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys pinouts and pin description stm32f437xx and stm32f439xx 77/240 docid024244 rev 10 port c pc8 - - tim3_ ch3 tim8_ ch3 -- - - usart6_ ck - - - sdio_d0 dcmi_ d2 - even tout pc9 mco2 - tim3_ ch4 tim8_ ch4 i2c3_ sda i2s_ ckin -- - - - -sdio_d1 dcmi_ d3 - even tout pc10 - - - - - - spi3_ sck/i2s 3_ck usart3_ tx uart4_tx - - - sdio_d2 dcmi_ d8 lcd_r2 even tout pc11 - - - - - i2s3ext _sd spi3_ miso usart3_ rx uart4_rx - - - sdio_d3 dcmi_ d4 - even tout pc12 - - - - - - spi3_ mosi/i2 s3_sd usart3_ ck uart5_tx - - - sdio_ck dcmi_ d9 - even tout pc13 - - - - - - - - - - - - - - - even tout pc14 - - - - - - - - - - - - - - - even tout pc15 - - - - - - - - - - - - - - - even tout port d pd0 - - - - - - - - - can1_rx - - fmc_d2 - - even tout pd1 - - - - - - - - - can1_tx - - fmc_d3 - - even tout pd2 - - tim3_ etr --- - -uart5_rx- - - sdio_ cmd dcmi_ d11 - even tout pd3 - - - - - spi2_s ck/i 2s2_ck - usart2_ cts - - - - fmc_clk dcmi_ d5 lcd_g7 even tout pd4 - - - - - - - usart2_ rts - - - - fmc_noe - - even tout pd5 - - - - - - - usart2_ tx ----fmc_nwe-- even tout pd6 - - - - - spi3_ mosi/i2 s3_sd sai1_ sd_a usart2_ rx ---- fmc_ nwait dcmi_ d10 lcd_b2 even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys stm32f437xx and stm32f439xx pinouts and pin description docid024244 rev 10 78/240 port d pd7 - - - - - - - usart2_ ck ---- fmc_ne1/ fmc_ nce2 -- even tout pd8 - - - - - - - usart3_ tx - - - - fmc_d13 - - even tout pd9 - - - - - - - usart3_ rx - - - - fmc_d14 - - even tout pd10 - - - - - - - usart3_ ck - - - - fmc_d15 - lcd_b3 even tout pd11 - - - - - - - usart3_ cts ----fmc_a16-- even tout pd12 - - tim4_ ch1 --- - usart3_ rts ----fmc_a17-- even tout pd13 - - tim4_ ch2 - - - - - - - - - fmc_a18 - - even tout pd14 - - tim4_ ch3 --- - - - - - -fmc_d0- - even tout pd15 - - tim4_ ch4 --- - - - - - -fmc_d1- - even tout port e pe0 - - tim4_ etr - - - - - uart8_rx - - - fmc_ nbl0 dcmi_ d2 - even tout pe1 - - - - - - - - uart8_tx - - - fmc_ nbl1 dcmi_ d3 - even tout pe2 trac eclk ---- spi4_ sck sai1_ mclk_a -- - - eth_mii_ txd3 fmc_a23 - - even tout pe3 trac ed0 ----- sai1_ sd_b - - - - - fmc_a19 - - even tout pe4 trac ed1 ---- spi4_ nss sai1_ fs_a - - - - - fmc_a20 dcmi_ d4 lcd_b0 even tout pe5 trac ed2 -- tim9_ ch1 - spi4_m iso sai1_ sck_a - - - - - fmc_a21 dcmi_ d6 lcd_g0 even tout pe6 trac ed3 -- tim9_ ch2 - spi4_ mosi sai1_ sd_a - - - - - fmc_a22 dcmi_ d7 lcd_g1 even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys pinouts and pin description stm32f437xx and stm32f439xx 79/240 docid024244 rev 10 port e pe7 - tim1_ etr - - - - - - uart7_rx - - - fmc_d4 - - even tout pe8 - tim1_ ch1n - - - - - - uart7_tx - - - fmc_d5 - - even tout pe9 - tim1_ ch1 - - - - - - - - - - fmc_d6 - - even tout pe10 - tim1_ ch2n - - - - - - - - - - fmc_d7 - - even tout pe11 - tim1_ ch2 --- spi4_ nss - - - - - - fmc_d8 - lcd_g3 even tout pe12 - tim1_ ch3n --- spi4_ sck - - - - - - fmc_d9 - lcd_b4 even tout pe13 - tim1_ ch3 --- spi4_ miso - - - - - - fmc_d10 - lcd_de even tout pe14 - tim1_ ch4 --- spi4_ mosi - - - - - - fmc_d11 - lcd_ clk even tout pe15 - tim1_ bkin - - - - - - - - - fmc_d12 - lcd_r7 even tout port f pf0 - - - - i2c2_ sda -- - - - - -fmc_a0- - even tout pf1 - i2c2_ scl -- - - - - -fmc_a1- - even tout pf2 - - - - i2c2_ smba -- - - - - -fmc_a2- - even tout pf3 - - - - - - - - - - - fmc_a3 - - even tout pf4 - - - - - - - - - - - fmc_a4 - - even tout pf5 - - - - - - - - - - - fmc_a5 - - even tout pf6 - - - tim10_ ch1 - spi5_ nss sai1_ sd_b - uart7_rx - - - fmc_ niord -- even tout pf7 - - - tim11_ ch1 - spi5_ sck sai1_ mclk_b -uart7_tx - - - fmc_ nreg -- even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys stm32f437xx and stm32f439xx pinouts and pin description docid024244 rev 10 80/240 port f pf8 - - - - - spi5_ miso sai1_ sck_b - - tim13_ch1 - - fmc_ niowr -- even tout pf9 - - - - - spi5_ mosi sai1_ fs_b - - tim14_ch1 - - fmc_cd - - even tout pf10 - - - - - - - - - - - - fmc_intr dcmi_ d11 lcd_de even tout pf11 - - - - - spi5_ mosi -- - - - - fmc_ sdnras dcmi_ d12 - even tout pf12 - - - - - - - - - - - - fmc_a6 - - even tout pf13 - - - - - - - - - - - - fmc_a7 - - even tout pf14 - - - - - - - - - - - - fmc_a8 - - even tout pf15 - - - - - - - - - - - - fmc_a9 - - even tout port g pg0 - - - - - - - - - - - - fmc_a10 - - even tout pg1 - - - - - - - - - - - - fmc_a11 - - even tout pg2 - - - - - - - - - - - - fmc_a12 - - even tout pg3 - - - - - - - - - - - - fmc_a13 - - even tout pg4 - - - - - - - - - - - - fmc_a14/ fmc_ba0 -- even tout pg5 - - - - - - - - - - - - fmc_a15/ fmc_ba1 -- even tout pg6 - - - - - - - - - - - - fmc_int2 dcmi_ d12 lcd_r7 even tout pg7 - - - - - - - - usart6_ ck ---fmc_int3 dcmi_ d13 lcd_ clk even tout pg8 - - - - - spi6_ nss -- usart6_ rts -- eth_pps _out fmc_sdc lk -- even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys pinouts and pin description stm32f437xx and stm32f439xx 81/240 docid024244 rev 10 port g pg9 - - - - - - - - usart6_ rx --- fmc_ne2/ fmc_ nce3 dcmi_ vsync (1) - even tout pg10 - - - - - - - - - lcd_g3 - - fmc_ nce4_1/ fmc_ne3 dcmi_ d2 lcd_b2 even tout pg11 - - - - - - - - - - - eth_mii_ tx_en/ eth_rmii _tx_en fmc_ nce4_2 dcmi_ d3 lcd_b3 even tout pg12 - - - - - spi6_ miso -- usart6_ rts lcd_b4 - - fmc_ne4 - lcd_b1 even tout pg13 - - - - - spi6_ sck -- usart6_ cts -- eth_mii_ txd0/ eth_rmii _txd0 fmc_a24 - - even tout pg14 - - - - - spi6_ mosi -- usart6_ tx -- eth_mii_ txd1/ eth_rmii _txd1 fmc_a25 - - even tout pg15 - - - - - - - - usart6_ cts --- fmc_ sdncas dcmi_ d13 - even tout port h ph0 - - - - - - - - - - - - - - - even tout ph1 - - - - - - - - - - - - - - - even tout ph2 - - - - - - - - - - - eth_mii_ crs fmc_ sdcke0 - lcd_r0 even tout ph3 - - - - - - - - - - - eth_mii_ col fmc_sdn e0 - lcd_r1 even tout ph4 - - - - i2c2_ scl -- - - - otg_hs_ ulpi_nxt ---- even tout ph5 - - - - i2c2_ sda spi5_n ss -- - - - - fmc_sdn we -- even tout ph6 - - - - i2c2_ smba spi5_ sck - - - tim12_ch1 - - fmc_ sdne1 dcmi_ d8 -- table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys stm32f437xx and stm32f439xx pinouts and pin description docid024244 rev 10 82/240 port h ph7 - - - - i2c3_ scl spi5_ miso -- - - - eth_mii_ rxd3 fmc_ sdcke1 dcmi_ d9 -- ph8 - - - - i2c3_ sda -- - - - - -fmc_d16 dcmi_ hsync lcd_r2 even tout ph9 - - - - i2c3_ smba - - - - tim12_ch2 - - fmc_d17 dcmi_ d0 lcd_r3 even tout ph10 - - tim5_ ch1 --- - - - - - -fmc_d18 dcmi_ d1 lcd_r4 even tout ph11 - - tim5_ ch2 --- - - - - - -fmc_d19 dcmi_ d2 lcd_r5 even tout ph12 - - tim5_ ch3 --- - - - - - -fmc_d20 dcmi_ d3 lcd_r6 even tout ph13 - - - tim8_ ch1n - - - - - can1_tx - - fmc_d21 - lcd_g2 even tout ph14 - - - tim8_ ch2n - - - - - - - - fmc_d22 dcmi_ d4 lcd_g3 even tout ph15 - - - tim8_ ch3n - - - - - - - - fmc_d23 dcmi_ d11 lcd_g4 even tout port i pi0 - - tim5_ ch4 -- spi2_ nss/i2 s2_ws - - - - - - fmc_d24 dcmi_ d13 lcd_g5 even tout pi1 - - - - - spi2_ sck/i2 s2_ck - - - - - - fmc_d25 dcmi_ d8 lcd_g6 even tout pi2 - - - tim8_ ch4 - spi2_ miso i2s2ext_ sd -- - --fmc_d26 dcmi_ d9 lcd_g7 even tout pi3 - - - tim8_ etr - spi2_m osi/i2s 2_sd fmc_d27 dcmi_d 10 even tout pi4 - - - tim8_ bkin -- - - - - - - fmc_ nbl2 dcmi_d 5 lcd_b4 even tout pi5 - - - tim8_ ch1 -- - - - - - - fmc_ nbl3 dcmi_ vsync lcd_b5 even tout pi6 - - - tim8_ ch2 - - - - - - - - fmc_d28 dcmi_ d6 lcd_b6 even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys pinouts and pin description stm32f437xx and stm32f439xx 83/240 docid024244 rev 10 port i pi7 - - - tim8_ ch3 - - - - - - - - fmc_d29 dcmi_ d7 lcd_b7 even tout pi8 - - - - - - - - - - - - - - - even tout pi9 - - - - - - - - - can1_rx - - fmc_d30 - lcd_ vsync even tout pi10 - - - - - - - - - - - eth_mii_ rx_er fmc_d31 - lcd_ hsync even tout pi11 - - - - - - - - - - otg_hs_ ulpi_dir ---- even tout pi12 - - - - - - - - - - - - - - lcd_ hsync even tout pi13 - - - - - - - - - - - - - - lcd_ vsync even tout pi14 - - - - - - - - - - - - - - lcd_ clk even tout pi15 - - - - - - - - - - - - - - lcd_r0 even tout port j pj0 - - - - - - - - - - - - - - lcd_r1 even tout pj1 - - - - - - - - - - - - - - lcd_r2 even tout pj2 - - - - - - - - - - - - - - lcd_r3 even tout pj3 - - - - - - - - - - - - - - lcd_r4 even tout pj4 - - - - - - - - - - - - - - lcd_r5 even tout pj5 - - - - - - - - - - - - - - lcd_r6 even tout pj6 - - - - - - - - - - - - - - lcd_r7 even tout pj7 - - - - - - - - - - - - - - lcd_g0 even tout table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys stm32f437xx and stm32f439xx pinouts and pin description docid024244 rev 10 84/240 port j pj8 - - - - - - - - - - - - - - lcd_g1 even tout pj9 - - - - - - - - - - - - - - lcd_g2 even tout pj10 - - - - - - - - - - - - - - lcd_g3 even tout pj11 - - - - - - - - - - - - - - lcd_g4 even tout pj12 - - - - - - - - - - - - - - lcd_b0 even tout pj13 - - - - - - - - - - - - - - lcd_b1 even tout pj14 - - - - - - - - - - - - - - lcd_b2 even tout pj15 - - - - - - - - - - - - - - lcd_b3 even tout port k pk0 - - - - - - - - - - - - - - lcd_g5 even tout pk1 - - - - - - - - - - - - - - lcd_g6 even tout pk2 - - - - - - - - - - - - - - lcd_g7 even tout pk3 - - - - - - - - - - - - - - lcd_b4 even tout pk4 - - - - - - - - - - - - - - lcd_b5 even tout pk5 - - - - - - - - - - - - - - lcd_b6 even tout pk6 - - - - - - - - - - - - - - lcd_b7 even tout pk7 - - - - - - - - - - - - - - lcd_de even tout 1. the dcmi_vsync alternate function on pg 9 is only available on silicon revision 3. table 12. stm32f437xx and stm32f439xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/ 10/11 i2c1/ 2/3 spi1/2/ 3/4/5/6 spi2/3/ sai1 spi3/ usart1/ 2/3 usart6/ uart4/5/7 /8 can1/2/ tim12/13/14 /lcd otg2_hs /otg1_ fs eth fmc/sdio /otg2_fs dcmi lcd sys docid024244 rev 10 85/240 stm32f437xx and stm32f439xx memory mapping 89 5 memory mapping the memory map is shown in figure 19 . figure 19. memory map 0 6 9 0 e \ w h % o r f n & r u w h [ 0 , q w h u q d o s h u l s k h u d o v 0 e \ w h % o r f n ) 0 & 0 e \ w h % o r f n ) 0 & e d q n w r e d q n [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ [ ) ) ) ) ) ) ) [ $ [ & ) ) ) ) ) ) ) [ ' [ ' ) ) ) ) ) ) ) [ ( [ ) ) ) ) ) ) ) ) 6 5 $ 0 . % d o l d v h g % \ e l w e d q g l q j 5 h v h u y h g [ [ % ) ) ) [ & [ ) ) ) ) [ [ ) ) ) ) ) ) ) [ 5 h v h u y h g [ ) ) ) [ [ ) ) ) ) [ 5 h v h u y h g [ & [ ) ) ) ) ) ) ) $ + % [ [ ' ) ) ) ) ) ) ) $ + % 6 5 $ 0 . % d o l d v h g % \ e l w e d q g l q j [ % ) ) [ 6 5 $ 0 . % d o l d v h g % \ e l w e d q g l q j [ [ ) ) ) ) $ 3 % $ 3 % [ % ) ) [ & [ ) ) ) ) 5 h v h u y h g [ [ ) ) ) ) ) ) ) [ ) ) ) ) $ + % 5 h v h u y h g ) o d v k p h p r u \ [ [ ) ) ) ) ) ) ) [ ) ) ) [ ) ) ) $ ) [ ) ) ) & [ ) ) ) & [ [ ) ) ) ) ) [ [ ) ) ) ) ) ) [ [ ) ) ) ) ) 6 \ v w h p p h p r u \ 5 h v h u y h g 5 h v h u y h g $ o l d v h g w r ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q w k h % 2 2 7 s l q v 2 s w l r q % \ w h v 5 h v h u y h g [ ) ) ) & ) [ ) ) ) ) ) ) ) [ ) ) ) $ [ ) ) ) ) ) ) 5 h v h u y h g & & 0 g d w d 5 $ 0 . % g d w d 6 5 $ 0 [ [ ) ) ) ) 5 h v h u y h g [ [ ) ) ( % ) ) ) [ ) ) ( & [ ) ) ( & 2 s w l r q e \ w h v 5 h v h u y h g [ ) ) ( & ) [ ) ) ( ) ) ) ) [ & r u w h [ 0 l q w h u q d o s h u l s k h u d o v [ ( [ ( ) ) ) ) ) 5 h v h u y h g [ ( [ ) ) ) ) ) ) ) ) 0 e \ w h % o r f n ) 0 & 0 e \ w h % o r f n ) 0 & e d q n w r e d q n 0 e \ w h % o r f n 3 h u l s k h u d o v 0 e \ w h % o r f n 6 5 $ 0 0 e \ w h % o r f n 6 5 $ 0 memory mapping stm32f437xx and stm32f439xx 86/240 docid024244 rev 10 table 13. stm32f437xx and stm32f439xx register boundary addresses bus boundary address peripheral 0xe00f ffff - 0xffff ffff reserved cortex-m4 0xe000 0000 - 0xe00f ffff cortex-m4 internal peripherals ahb3 0xd000 0000 - 0xdfff ffff fmc bank 6 0xc000 0000 - 0xcfff ffff fmc bank 5 0xa000 1000 - 0xbfff ffff reserved 0xa000 0000- 0xa000 0fff fmc control register 0x9000 0000 - 0x9fff ffff fmc bank 4 0x8000 0000 - 0x8fff ffff fmc bank 3 0x7000 0000 - 0x7fff ffff fmc bank 2 0x6000 0000 - 0x6fff ffff fmc bank 1 0x5006 0c00- 0x5fff ffff reserved ahb2 0x5006 0800 - 0x5006 0bff rng 0x5006 0400 - 0x5006 07ff hash 0x5006 0000 - 0x5006 03ff cryp 0x5005 0400 - x5006 07ff reserved 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000- 0x5004 ffff reserved 0x5000 0000 - 0x5003 ffff usb otg fs docid024244 rev 10 87/240 stm32f437xx and stm32f439xx memory mapping 89 0x4008 0000- 0x4fff ffff reserved ahb1 0x4004 0000 - 0x4007 ffff usb otg hs 0x4002 bc00- 0x4003 ffff reserved 0x4002 b000 - 0x4002 bbff dma2d 0x4002 9400 - 0x4002 afff reserved 0x4002 9000 - 0x4002 93ff ethernet mac 0x4002 8c00 - 0x4002 8fff 0x4002 8800 - 0x4002 8bff 0x4002 8400 - 0x4002 87ff 0x4002 8000 - 0x4002 83ff 0x4002 6800 - 0x4002 7fff reserved 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 5fff reserved 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2c00 - 0x4002 2fff reserved 0x4002 2800 - 0x4002 2bff gpiok 0x4002 2400 - 0x4002 27ff gpioj 0x4002 2000 - 0x4002 23ff gpioi 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1800 - 0x4002 1bff gpiog 0x4002 1400 - 0x4002 17ff gpiof 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa table 13. stm32f437xx and stm32f439xx register boundary addresses (continued) bus boundary address peripheral memory mapping stm32f437xx and stm32f439xx 88/240 docid024244 rev 10 0x4001 6c00- 0x4001 ffff reserved apb2 0x4001 6800 - 0x4001 6bff lcd-tft 0x4001 5c00 - 0x4001 67ff reserved 0x4001 5800 - 0x4001 5bff sai1 0x4001 5400 - 0x4001 57ff spi6 0x4001 5000 - 0x4001 53ff spi5 0x4001 4c00 - 0x4001 4fff reserved 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff spi4 0x4001 3000 - 0x4001 33ff spi1 0x4001 2c00 - 0x4001 2fff sdio 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 table 13. stm32f437xx and stm32f439xx register boundary addresses (continued) bus boundary address peripheral docid024244 rev 10 89/240 stm32f437xx and stm32f439xx memory mapping 89 0x4000 8000- 0x4000 ffff reserved apb1 0x4000 7c00 - 0x4000 7fff uart8 0x4000 7800 - 0x4000 7bff uart7 0x4000 7400 - 0x4000 77ff dac 0x4000 7000 - 0x4000 73ff pwr 0x4000 6c00 - 0x4000 6fff reserved 0x4000 6800 - 0x4000 6bff can2 0x4000 6400 - 0x4000 67ff can1 0x4000 6000 - 0x4000 63ff reserved 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 5000 - 0x4000 53ff uart5 0x4000 4c00 - 0x4000 4fff uart4 0x4000 4800 - 0x4000 4bff usart3 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff i2s3ext 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff i2s2ext 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2bff rtc & bkp registers 0x4000 2400 - 0x4000 27ff reserved 0x4000 2000 - 0x4000 23ff tim14 0x4000 1c00 - 0x4000 1fff tim13 0x4000 1800 - 0x4000 1bff tim12 0x4000 1400 - 0x4000 17ff tim7 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 table 13. stm32f437xx and stm32f439xx register boundary addresses (continued) bus boundary address peripheral electrical characteristics stm32f437xx and stm32f439xx 90/240 docid024244 rev 10 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.7 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 20 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 21 . figure 20. pin loading conditi ons figure 21. pin input voltage - 3 6 # p & - # 5 p i n - 3 6 - # 5 p i n 6 ) . docid024244 rev 10 91/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.1.6 power supply scheme figure 22. power supply scheme 1. to connect bypass_reg and pdr_on pins, refer to section 3.17: power supply supervisor and section 3.18: voltage regulator 2. the two 2.2 f ceramic capacitors should be replaced by tw o 100 nf decoupling capacitors when the voltage regulator is off. 3. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. 4. v dda =v dd and v ssa =v ss . caution: each power supply pair (v dd /v ss , v dda /v ssa ...) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure good operation of the device. it is not recommended to remove filterin g capacitors to reduce pcb size or cost. this might cause incorrect operation of the device. 0 6 9 % d f n x s f l u f x l w u \ 2 6 & . 5 7 & : d n h x s o r j l f % d f n x s u h j l v w h u v e d f n x s 5 $ 0 . h u q h o o r j l f & 3 8 g l j l w d o 5 $ 0 $ q d o r j 5 & v 3 / / 3 r z h u v z l w f k 9 % $ 7 * 3 , 2 v 2 8 7 , 1 ? q ) ? ? ) 9 % $ 7 w r 9 9 r o w d j h u h j x o d w r u 9 ' ' $ $ ' & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) ) o d v k p h p r u \ 9 & $ 3 b 9 & $ 3 b ? ? ) % < 3 $ 6 6 b 5 ( * 3 ' 5 b 2 1 5 h v h w f r q w u r o o h u 9 ' ' 9 6 6 9 ' ' 9 5 ( ) 9 5 ( ) 9 6 6 $ 9 5 ( ) q ) ? ) electrical characteristics stm32f437xx and stm32f439xx 92/240 docid024244 rev 10 6.1.7 current consumption measurement figure 23. current consum ption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 14: voltage characteristics , table 15: current characteristics , and table 16: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. device mission profile (application condit ions) is compliant with jedec jesd47 qualification standard, extended miss ion profiles are available on demand. d l 9 % $ 7 9 ' ' 9 ' ' $ , ' ' b 9 % $ 7 , ' ' table 14. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd and vbat) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ? 0.3 4.0 v v in input voltage on ft pins (2) 2. v in maximum value must always be respected. refer to table 15 for the values of the maximum allowed injected current. v ss ? 0.3 v dd +4.0 input voltage on tta pins v ss ? 0.3 4.0 input voltage on any other pin v ss ? 0.3 4.0 input voltage on boot0 pin v ss 9.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins including v ref- -50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.15: absolute maximum ratings (electrical sensitivity) docid024244 rev 10 93/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 15. current characteristics symbol ratings max. unit i vdd total current into sum of all v dd_x power lines (source) (1) 270 ma i vss total current out of sum of all v ss_x ground lines (sink) (1) ? 270 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss_x ground line (sink) (1) ? 100 i io output current sunk by any i/o and control pin 25 output current sourced by any i/os and control pin ? 25 i io total output current sunk by sum of all i/o and control pins (2) 120 total output current sourced by sum of all i/os and control pins (2) ? 120 i inj(pin) (3) injected current on ft pins (4) ? 5/+0 injected current on nrst and boot0 pins (4) injected current on tta pins (5) 5 i inj(pin) (5) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to t he external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the to tal output current must not be sunk/sourced between two c onsecutive power supply pins referrin g to high pin count lqfp packages. 3. negative injection disturbs the analog performance of the device. see note in section 6.3.21: 12-bit adc characteristics . 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. a positive injection is induced by v in >v dda while a negative inject ion is induced by v in docid024244 rev 10 95/240 stm32f437xx and stm32f439xx electrical characteristics 198 v in input voltage on rst and ft pins (7) 2v v dd 3.6 v ? 0.3 - 5.5 v v dd 2v ? 0.3 - 5.2 input voltage on tta pins ? 0.3 - v dda + 0.3 input voltage on boot0 pin 0 - 9 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (8) lqfp100 - - 465 mw wlcsp143 - - 641 lqfp144 - - 500 ufbga169 - - 385 lqfp176 - - 526 ufbga176 - - 513 lqfp208 - - 1053 tfbga216 - - 690 t a ambient temperature for 6 suffix version maximum power dissipation ? 40 85 c low power dissipation (9) ? 40 105 ambient temperature for 7 suffix version maximum power dissipation ? 40 105 c low power dissipation (9) ? 40 125 t j junction temperature range 6 suffix version ? 40 105 c 7 suffix version ? 40 125 1. the over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 v. 2. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.17.2: internal reset off ). 3. when the adc is used, refer to table 74: adc characteristics . 4. if v ref+ pin is present, it must res pect the following condition: v dda -v ref+ < 1.2 v. 5. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 6. the over-drive mode is not supported when the internal regulator is off. 7. to sustain a voltage higher than vdd+0.3, the internal pull-up and pull-down re sistors must be disabled 8. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 9. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 17. general operating conditions (continued) symbol parameter conditions (1) min typ max unit electrical characteristics stm32f437xx and stm32f439xx 96/240 docid024244 rev 10 6.3.2 vcap1/vcap2 external capacitor stabilization for the main regula tor is achieved by connecting an external capacitor c ext to the vcap1/vcap2 pins. c ext is specified in table 19 . figure 24. external capacitor c ext 1. legend: esr is the equivalent series resistance. table 18. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum hclk frequency vs flash memory wait states (1)(2) i/o operation possible flash memory operations v dd =1.7 to 2.1 v (3) conversion time up to 1.2 msps 20 mhz (4) 168 mhz with 8 wait states and over-drive off no i/o compensation 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 22 mhz 180 mhz with 8 wait states and over-drive on no i/o compensation 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 180 mhz with 7 wait states and over-drive on i/o compensation works 16-bit erase and program operations v dd = 2.7 to 3.6 v (5) conversion time up to 2.4 msps 30 mhz 180 mhz with 5 wait states and over-drive on i/o compensation works 32-bit erase and program operations 1. applicable only when the code is executed from flash memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.17.2: internal reset off ). 4. prefetch is not available. 5. the voltage range for usb full speed phys can drop down to 2.7 v. however the electrical characteristics of d- and d+ pins will be degraded between 2.7 and 3 v. table 19. vcap1/vcap2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter conditions cext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 0 6 9 ( 6 5 5 / h d n & docid024244 rev 10 97/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.3 operating conditi ons at power-up / powe r-down (regulator on) subject to general operating conditions for t a . table 20. operating conditions at power-up / power-down (regulator on) 6.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 table 21. operating conditions at pow er-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20 electrical characteristics stm32f437xx and stm32f439xx 98/240 docid024244 rev 10 6.3.5 reset and power cont rol block characteristics the parameters given in table 22 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . table 22. reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (risi ng edge) 2.54 2.60 2.65 v pls[2:0]=011 (fallin g edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 2.92 v pls[2:0]=110 (risi ng edge) 2.96 3.03 3.10 v pls[2:0]=110 (fallin g edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (fallin g edge) 2.95 3.03 3.09 v v pvdhyst (1) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 1.68 1.76 v rising edge 1.64 1.72 1.80 v v pdrhyst (1) pdr hysteresis - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v v borhyst (1) bor hysteresis - 100 - mv t rsttempo (1)(2) por reset temporization 0.5 1.5 3.0 ms docid024244 rev 10 99/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.6 over-drive switching characteristics when the over-drive mode switches from enabl ed to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. the over-drive switching c haracteristics are given in table 23 . they are sbject to general operating conditions for t a . i rush (1) inrush current on voltage regulator power- on (por or wakeup from standby) - 160 200 ma e rush (1) inrush energy on voltage regulator power- on (por or wakeup from standby) v dd = 1.7 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. guaranteed by design. 2. the reset temporization is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 22. reset and power control block characteristics (continued) symbol parameter conditions min typ max unit table 23. over-drive switching characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit tod_swen over_drive switch enable time hsi - 45 - s hse max for 4 mhz and min for 26 mhz 45 - 100 external hse 50 mhz - 40 - tod_swdis over_drive switch disable time hsi - 20 - hse max for 4 mhz and min for 26 mhz. 20 - 80 external hse 50 mhz - 15 - electrical characteristics stm32f437xx and stm32f439xx 100/240 docid024244 rev 10 6.3.7 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 23: current consumption measurement scheme . all the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consum ption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load). ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted both to f hclk frequency and v dd range (see table 18: limitations depending on the operating power supply range ). ? regulator on ? the voltage scaling and over-drive mode are adjusted to f hclk frequency as follows: ? scale 3 for f hclk 120 mhz ? scale 2 for 120 mhz < f hclk 144 mhz ? scale 1 for 144 mhz < f hclk 180 mhz. the over-drive is only on at 180 mhz. ? the system clock is hclk, f pclk1 = f hclk /4, and f pclk2 = f hclk /2. ? external clock frequency is 4 mhz and pll is on when f hclk is higher than 25 mhz. ? the maximum values are obtained for v dd = 3.6 v and a maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. docid024244 rev 10 101/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 24. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram (1) symbol parameter conditions f hclk (mhz) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode all peripherals enabled (3)(4) 180 98 104 (5) 123 141 (5) ma 168 89 98 (5) 116 133 (5) 150 75 84 100 115 144 72 81 96 112 120 54 58 72 85 90 43 45 56 66 60 29 30 38 45 30 16 20 34 46 25 13 16 30 43 16 11 13 27 39 8592336 4482134 2272033 all peripherals disabled (3) 180 44 47 (5) 69 87 (5) 168 41 45 (5) 66 83 (5) 150 36 39 57 73 144 33 37 56 72 120 25 29 43 56 90 20 21 32 41 60 14 15 22 28 30 8 8 12 26 25 7 7 10 24 16 7 9 22 35 8372134 4362033 2262033 1. code and data processing running from sram1 using boot pins. 2. guaranteed by characterization. 3. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 4. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.6 ma per adc for the analog part. 5. guaranteed by test in production. electrical characteristics stm32f437xx and stm32f439xx 102/240 docid024244 rev 10 table 25. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator disabled) symbol parameter conditions f hclk (mhz) typ max (1) unit ta= 25 c ta=85 c ta=105 c i dd supply current in run mode all peripherals enabled (2)(3) 180 103 112 140 151 ma 168 98 107 126 144 150 87 95 112 128 144 85 92 108 124 120 66 71 85 99 90 54 58 69 80 60 37 39 47 55 30 20 24 39 51 25 17 21 35 48 16 12 16 30 42 87112437 4582235 2372134 all peripherals disabled (3) 180 57 62 87 106 168 50 54 76 93 150 46 50 70 86 144 45 49 68 84 120 36 41 56 69 90 29 34 46 57 60 21 24 33 41 30 13 17 31 44 25 11 15 28 41 16 8 12 25 38 8592335 4472134 236.52033 1. guaranteed by characterizati on unless otherwise specified. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 register ), add an additional power consumption of 1.6 ma per adc for the analog part. docid024244 rev 10 103/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 26. typical and maximum current consumption in sleep mode symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode all peripherals enabled (2) 180 78 89 (3) 110 130 (3) ma 168 66 75 (3) 93 110 (3) 150 56 618096 144 54 587894 120 40 445972 90 32 34 46 56 60 22 23 31 38 30 10 16 30 43 25 9 142840 16 5 122540 8382235 4372134 226.52033 all peripherals disabled 180 21 26 (3) 54 76 (3) 168 16 20 (3) 41 58 (3) 150 14 173652 144 13 16.5 35 51 120 10 142841 90 8 132637 60 6 9 17 25 30 5 8 22 35 25 3 7 21 34 16 3 7 21 34 8262033 4262033 2262033 1. guaranteed by characterizati on unless otherwise specified. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. based on characterization, tested in production. electrical characteristics stm32f437xx and stm32f439xx 104/240 docid024244 rev 10 table 27. typical and maximum current consumptions in stop mode symbol parameter conditions typ max (1) unit v dd = 3.6 v t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop_nm (normal mode) supply current in stop mode with voltage regulator in main regulator mode flash memory in stop mode, all oscillators off, no independent watchdog 0.40 1.50 14.00 25.00 ma flash memory in deep power down mode, all oscillators off, no independent watchdog 0.35 1.50 14.00 25.00 supply current in stop mode with voltage regulator in low power regulator mode flash memory in stop mode, all oscillators off, no independent watchdog 0.29 1.10 10.00 18.00 flash memory in deep power down mode, all oscillators off, no independent watchdog 0.23 1.10 10.00 18.00 i dd_stop_udm (under-drive mode) supply current in stop mode with voltage regulator in main regulator and under- drive mode flash memory in deep power down mode, main regulator in under-drive mode, all oscillators off, no independent watchdog 0.19 0.50 6.00 9.00 supply current in stop mode with voltage regulator in low power regulator and under- drive mode flash memory in deep power down mode, low power regulator in under-drive mode, all oscillators off, no independent watchdog 0.10 0.40 4.00 7.00 1. data based on characterization, tested in production. docid024244 rev 10 105/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 28. typical and maximum current consumptions in standby mode symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c v dd = 1.7 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_stby supply current in standby mode backup sram on, low-speed oscillator (lse) and rtc on 2.80 3.00 3.60 7.00 19.00 36.00 a backup sram off, low- speed oscillator (lse) and rtc on 2.30 2.60 3.10 6.00 16.00 31.00 backup sram on, rtc and lse off 2.30 2.50 2.90 6.00 (3) 18.00 (3) 35.00 (3) backup sram off, rtc and lse off 1.70 1.90 2.20 5.00 (3) 15.00 (3) 30.00 (3) 1. the typical current consumption values are given with pdr off (internal reset o ff). when the pdr is off (internal reset off), the typical current consumpt ion is reduced by additional 1.2 a. 2. based on characterization, not tested in production unless otherwise specified. 3. based on characterization, tested in production. table 29. typical and maximum current consumptions in v bat mode symbol parameter conditions (1) typ max (2) unit t a = 25 c t a = 85 c t a = 105 c v bat = 1.7 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vbat backup domain supply current backup sram on, low-speed oscillator (lse) and rtc on 1.28 1.40 1.62 6 11 a backup sram off, low-speed oscillator (lse) and rtc on 0.66 0.76 0.97 3 5 backup sram on, rtc and lse off 0.70 0.72 0.74 5 10 backup sram off, rtc and lse off 0.10 0.10 0.10 2 4 1. crystal used: abracon abs07-120-32.768 khz-t with a c l of 6 pf for typical values. 2. guaranteed by characterization results. electrical characteristics stm32f437xx and stm32f439xx 106/240 docid024244 rev 10 figure 25. typical v bat current consumption (lse and rtc on/backup ram off) figure 26. typical v bat current consumption (lse and rtc on/backup ram on) - 3 6 ? # ? # ? # ? # ? # ) $ $ ? 6 " ! 4 ? ! 4 e m p e r a t u r e 6 6 6 6 6 6 6 6 6 - 3 6 ) $ $ ? 6 " ! 4 ? ! 4 e m p e r a t u r e ? # ? # ? # ? # ? # 6 6 6 6 6 6 6 6 6 docid024244 rev 10 107/240 stm32f437xx and stm32f439xx electrical characteristics 198 additional current consumption the mcu is placed under the following conditions: ? all i/o pins are configured in analog mode. ? the flash memory access time is adjusted to fhclk frequency. ? the voltage scaling is adjusted to fhclk frequency as follows: ? scale 3 for f hclk 120 mhz, ? scale 2 for 120 mhz < f hclk 144 mhz ? scale 1 for 144 mhz < f hclk 180 mhz. the over-drive is only on at 180 mhz. ? the system clock is hclk, f pclk1 = f hclk /4, and f pclk2 = f hclk /2. ? hse crystal clock frequency is 25 mhz. ? when the regulator is off, v12 is provided externally as described in table 17: general operating conditions ? t a = 25 c . table 30. typical current consumption in run mode, code with data processing running from flash memory or ram, regulator on (art accelerator enabled except prefetch), v dd =1.7 v (1) symbol parameter conditions f hclk (mhz) typ unit i dd supply current in run mode from v dd supply all peripheral enabled 168 88.2 ma 150 74.3 144 71.3 120 52.9 90 42.6 60 28.6 30 15.7 25 12.3 all peripheral disabled 168 40.6 150 30.6 144 32.6 120 24.7 90 19.7 60 13.6 30 7.7 25 6.7 1. when peripherals are enabled, the power consumption correspondi ng to the analog part of the peripherls (such as adc, or dac) is not included. electrical characteristics stm32f437xx and stm32f439xx 108/240 docid024244 rev 10 table 31. typical current consumption in run mode, code with data processing running from flash memory, regulator off (art accelerator enabled except prefetch) (1) symbol parameter conditions f hclk (mhz) vdd=3.3v vdd=1.7v unit i dd12 i dd i dd12 i dd i dd12 / i dd supply current in run mode from v 12 and v dd supply all peripherals enabled 168 77.8 1.3 76.8 1.0 ma 150 70.8 1.3 69.8 1.0 144 64.5 1.3 63.6 1.0 120 49.9 1.2 49.3 0.9 90 39.2 1.3 38.7 1.0 60 27.2 1.2 26.8 0.9 30 15.6 1.2 15.4 0.9 25 13.6 1.2 13.5 0.9 all peripherals disabled 168 38.2 1.3 37.0 1.0 150 34.6 1.3 33.4 1.0 144 31.3 1.3 30.3 1.0 120 24.0 1.2 23.2 0.9 90 18.1 1.4 18.0 1.0 60 12.9 1.2 12.5 0.9 30 7.2 1.2 6.9 0.9 25 6.3 1.2 6.1 0.9 1. when peripherals are enabled, the power consumption correspon ding to the analog part of the peripherals (such as adc, or dac) is not included. docid024244 rev 10 109/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 32. typical current consumption in sleep mode, regulator on, v dd =1.7 v (1) symbol parameter conditions f hclk (mhz) typ unit i dd supply current in sleep mode from v dd supply all peripherals enabled 168 65.5 ma 150 55.5 144 53.5 120 39.0 90 31.6 60 21.7 30 9.8 25 8.8 all peripherals disabled 168 15.7 150 13.7 144 12.7 120 9.7 90 7.7 60 5.7 30 4.7 25 2.8 1. when peripherals are enabled, the power c onsumption corresponding to the analog part of the peripherals (such as adc, or dac) is not included. electrical characteristics stm32f437xx and stm32f439xx 110/240 docid024244 rev 10 table 33. tyical current consumption in sleep mode, regulator off (1) symbol parameter conditions f hclk (mhz) vdd=3.3 v vdd=1.7 v unit i dd12 i dd i dd12 i dd i dd12 /i dd supply current in sleep mode from v 12 and v dd supply all peripherals enabled 180 61.5 1.4 - - ma 168 59.4 1.3 59.4 1.0 150 53.9 1.3 53.9 1.0 144 49.0 1.3 49.0 1.0 120 38.0 1.2 38.0 0.9 90 29.3 1.4 29.3 1.1 60 20.2 1.2 20.2 0.9 30 11.9 1.2 11.9 0.9 25 10.4 1.2 10.4 0.9 all peripherals disabled 180 14.9 1.4 - - 168 14.0 1.3 14.0 1.0 150 12.6 1.3 12.6 1.0 144 11.5 1.3 11.5 1.0 120 8.7 1.2 8.7 0.9 90 7.1 1.4 7.1 1.1 60 5.0 1.2 5.0 0.9 30 3.1 1.2 3.1 0.9 25 2.8 1.2 2.8 0.9 1. when peripherals are enabled, the power c onsumption corresponding to the analog part of the peripherals (such as adc, or dac) is not included. docid024244 rev 10 111/240 stm32f437xx and stm32f439xx electrical characteristics 198 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 56: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 35: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = electrical characteristics stm32f437xx and stm32f439xx 112/240 docid024244 rev 10 table 34. switching output i/o current consumption (1) 1. c s is the pcb board capacitance including the pad pin. c s = 7 pf (estimated value). symbol parameter conditions i/o toggling frequency (fsw) typ unit i ddio i/o switching current v dd = 3.3 v c= c int (2) 2. this test is performed by cutting the lqfp176 package pin (pad removal). 2 mhz 0.0 ma 8 mhz 0.2 25 mhz 0.6 50 mhz 1.1 60 mhz 1.3 84 mhz 1.8 90 mhz 1.9 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.1 8 mhz 0.4 25 mhz 1.23 50 mhz 2.43 60 mhz 2.93 84 mhz 3.86 90 mhz 4.07 i ddio i/o switching current v dd = 3.3 v c ext = 10 pf c = c int + c ext + c s 2 mhz 0.18 ma 8 mhz 0.67 25 mhz 2.09 50 mhz 3.6 60 mhz 4.5 84 mhz 7.8 90 mhz 9.8 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.26 8 mhz 1.01 25 mhz 3.14 50 mhz 6.39 60 mhz 10.68 v dd = 3.3 v c ext = 33 pf c = c int + cext + c s 2 mhz 0.33 8 mhz 1.29 25 mhz 4.23 50 mhz 11.02 docid024244 rev 10 113/240 stm32f437xx and stm32f439xx electrical characteristics 198 on-chip peripheral current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are in analog input configuration. ? all peripherals are disabled unless otherwise mentioned. ? i/o compensation cell enabled. ? the art accelerator is on. ? scale 1 mode selected, internal digital voltage v12 = 1.32 v. ? hclk is the system clock. f pclk1 = f hclk /4, and f pclk2 = f hclk /2. the given value is calculated by measur ing the difference of current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ?f hclk = 180 mhz (scale1 + over-drive on), f hclk = 144 mhz (scale 2), f hclk = 120 mhz (scale 3)" ? ambient operating temperature is 25 c and v dd =3.3 v. table 35. peripheral current consumption peripheral i dd ( typ) (1) unit scale 1 scale 2 scale 3 ahb1 (up to 180 mhz) gpioa 2.50 2.36 2.08 a/mhz gpiob 2.56 2.36 2.08 gpioc 2.44 2.29 2.00 gpiod 2.50 2.36 2.08 gpioe 2.44 2.29 2.00 gpiof 2.44 2.29 2.00 gpiog 2.39 2.22 2.00 gpioh 2.33 2.15 1.92 gpioi 2.39 2.22 2.00 gpioj 2.33 2.15 1.92 gpiok 2.33 2.15 1.92 otg_hs+ulpi 27.00 24.86 21.92 crc 0.44 0.42 0.33 bkpsram 0.78 0.69 0.58 dma1 25.33 23.26 20.50 dma2 24.72 22.71 20.00 dma2d 28.50 26.32 23.33 eth_mac eth_mac_tx eth_mac_rx eth_mac_ptp 21.56 20.07 17.75 electrical characteristics stm32f437xx and stm32f439xx 114/240 docid024244 rev 10 ahb2 (up to 180 mhz) otg_fs 25.67 26.67 23.58 a/mhz dcmi 3.72 3.40 3.00 rng 2.28 2.36 2.17 hash 4.39 4.03 3.58 crypto 3.00 2.78 2.42 ahb3 (up to 180 mhz) fmc 21.39 19.79 17.50 a/mhz bus matrix (2) 14.06 13.19 11.75 a/mhz table 35. peripheral current consumption (continued) peripheral i dd ( typ) (1) unit scale 1 scale 2 scale 3 docid024244 rev 10 115/240 stm32f437xx and stm32f439xx electrical characteristics 198 apb1 (up to 45 mhz) tim2 17.56 16.42 14.47 a/mhz tim3 14.22 13.36 11.80 tim4 14.89 13.64 12.13 tim5 17.33 16.42 14.47 tim6 2.89 2.53 2.47 tim7 3.11 2.81 2.47 tim12 7.33 6.97 6.13 tim13 4.89 4.47 4.13 tim14 5.56 5.31 4.80 pwr 11.11 10.31 9.13 usart2 4.22 3.92 3.47 usart3 4.44 4.19 3.80 uart4 4.00 3.92 3.47 uart5 4.00 3.92 3.47 uart7 4.00 3.92 3.47 uart8 3.78 3.92 3.47 i2c1 4.00 3.92 3.47 i2c2 4.00 3.92 3.47 i2c3 4.00 3.92 3.47 spi2 (3) 3.11 3.08 2.80 spi3 (3) 3.56 3.36 3.13 i2s2 2.89 2.81 2.47 i2s3 3.33 3.08 2.80 can1 6.89 6.42 5.80 can2 6.67 6.14 5.47 dac (4) 2.89 2.25 2.13 wwdg 0.89 0.86 0.80 table 35. peripheral current consumption (continued) peripheral i dd ( typ) (1) unit scale 1 scale 2 scale 3 electrical characteristics stm32f437xx and stm32f439xx 116/240 docid024244 rev 10 apb2 (up to 90 mhz) sdio 8.11 8.75 7.83 a/mhz tim1 17.11 15.97 14.17 tim8 17.33 16.11 14.33 tim9 7.22 6.67 6.00 tim10 4.56 4.31 3.83 tim11 4.78 4.44 4.00 adc1 (5) 4.67 4.31 3.83 adc2 (5) 4.78 4.44 4.00 adc3 (5) 4.56 4.17 3.67 spi1 1.44 1.39 1.17 usart1 4.00 3.75 3.33 usart6 4.00 3.75 3.33 spi4 1.44 1.39 1.17 spi5 1.44 1.39 1.17 spi6 1.44 1.39 1.17 syscfg 0.78 0.69 0.67 lcd_tft 39.89 37.22 33.17 sai1 3.78 3.47 3.17 1. when the i/o compensation cell is on, i dd typical value increases by 0.22 ma. 2. the busmatrix is automatically active when at least one master is on. 3. to enable an i2s peripheral, first set the i2smod bit and then the i2se bit in the spi_i2scfgr register. 4. when the dac is on and en1/2 bits are set in da c_cr register, add an additional power consumption of 0.8 ma per dac channel for the analog part. 5. when the adc is on (adon bit set in the adc_cr 2 register), add an additional power consumption of 1.6 ma per adc for the analog part. table 35. peripheral current consumption (continued) peripheral i dd ( typ) (1) unit scale 1 scale 2 scale 3 docid024244 rev 10 117/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.8 wakeup time from low-power modes the wakeup times given in table 36 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep modes: the wakeup event is wfe. ? wkup (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd =3.3 v. table 36. low-power mode wakeup timings symbol parameter conditions typ (1) max (1) unit t wusleep (2) wakeup from sleep - 6 - cpu clock cycle t wustop (2) wakeup from stop mode with mr/lp regulator in normal mode main regulator is on 13.6 - s main regulator is on and flash memory in deep power down mode 93 111 low power regulator is on 22 32 low power regulator is on and flash memory in deep power down mode 103 126 t wustop (2) wakeup from stop mode with mr/lp regulator in under-drive mode main regulator in under-drive mode (flash memory in deep power-down mode) 105 128 low power regulator in under-drive mode (flash memory in deep power-down mode ) 125 155 twustdby (2)(3) wakeup from standby mode 318 412 1. guaranteed by characterization results. 2. the wakeup times are measured from the wakeup event to the point in which the appl ication code reads the first 3. t wustdby maximum value is given at ?40 c. electrical characteristics stm32f437xx and stm32f439xx 118/240 docid024244 rev 10 6.3.9 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 56: i/o static characteristics . however, the recommended clock input waveform is shown in figure 27 . the characteristics given in table 37 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 17 . table 37. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 1-50mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a docid024244 rev 10 119/240 stm32f437xx and stm32f439xx electrical characteristics 198 low-speed external user clock generated from an external source in bypass mode the lse oscillato r is switched off and the inpu t pin is a standard i/o. the external clock signal has to respect the table 56: i/o static characteristics . however, the recommended clock input waveform is shown in figure 28 . the characteristics given in table 38 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 17 . figure 27. high-speed external clock source ac timing diagram table 38. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5-pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design. a i / 3 # ? ) . % x t e r n a l 3 4 - & c l o c k s o u r c e 6 ( 3 % ( t f ( 3 % t 7 ( 3 % ) , 4 ( 3 % t t r ( 3 % t 7 ( 3 % f ( 3 % ? e x t 6 ( 3 % , electrical characteristics stm32f437xx and stm32f439xx 120/240 docid024244 rev 10 figure 28. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 39 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). table 39. hse 4-26 mhz oscillator characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf@25 mhz - 450 - a v dd =3.3 v, esr= 30 ? , c l =10 pf@25 mhz - 530 - acc hse (2) 2. this parameter depends on the crystal used in the application. the minimum and maximum values must be respected to comply with usb standard specifications. hse accuracy ? 500 - 500 ppm g m _crit_max maximum critical crystal g m startup - - 1 ma/v t su(hse (3) 3. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is based on char acterization and not tested in production. it is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms d l 2 6 & b , 1 ( [ w h u q d o 6 7 0 ) f o r f n v r x u f h 9 / 6 ( + w i / 6 ( w : / 6 ( , / 7 / 6 ( w w u / 6 ( w : / 6 ( i / 6 ( b h [ w 9 / 6 ( / docid024244 rev 10 121/240 stm32f437xx and stm32f439xx electrical characteristics 198 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 29 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 29. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 40 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . table 40. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design. symbol parameter conditions min typ max unit r f feedback resistor - 18.4 - m i dd lse current consumption - - 1 a acc lse (2) 2. this parameter depends on the crystal used in t he application. refer to application note an2867. lse accuracy ? 500 - 500 ppm g m _crit_max maximum critical crystal g m startup - - 0.56 a/v t su(lse) (3) 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is based on characterization and not tested in production. it is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - s d l 2 6 & b 2 8 7 2 6 & b , 1 i + 6 ( & / 5 ) 6 7 0 ) 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q 5 ( ; 7 & / electrical characteristics stm32f437xx and stm32f439xx 122/240 docid024244 rev 10 figure 30. typical applicati on with a 32.768 khz crystal 6.3.10 internal clock source characteristics the parameters given in table 41 and table 42 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 17 . high-speed internal (hsi) rc oscillator d l 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / 5 ) 6 7 0 ) n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v % l d v f r q w u r o o h g j d l q & / table 41. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hsi hsi user-trimming step (2) 2. guaranteed by design. ---1% accuracy of the hsi oscillator t a = ?40 to 105 c (3) 3. guaranteed by characterization results. ? 8-4.5% t a = ?10 to 85 c (3) ? 4- 4 % t a = 25 c (4) 4. factory calibrated, parts not soldered. ? 1- 1 % t su(hsi) (2) hsi oscillator startup time - - 2.2 4 s i dd(hsi) (2) hsi oscillator power consumption - - 60 80 a docid024244 rev 10 123/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 31. acchsi accuracy versus temperature 1. guaranteed by characterization results. low-speed internal (lsi) rc oscillator table 42. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed by characterization results. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a 0 6 y 9 $ & & + 6 , 7 $ ? & 0 l q 0 d [ 7 \ s l f d o electrical characteristics stm32f437xx and stm32f439xx 124/240 docid024244 rev 10 figure 32. acc lsi versus temperature 6.3.11 pll characteristics the parameters given in table 43 and table 44 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 17 . - 3 6 . o r m a l i z e d d e v i a t i o n 4 e m p e r a t u r e ? # m a x a v g m i n table 43. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) 0.95 (2) 12.10mhz f pll_out pll multiplier output clock 24 - 180 mhz f pll48_out 48 mhz pll multiplier output clock -48 75mhz f vco_out pll vco output 100 - 432 mhz t lock pll lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 docid024244 rev 10 125/240 stm32f437xx and stm32f439xx electrical characteristics 198 jitter (3) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32 - main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples -330 - i dd(pll) (4) pll power consumption on vdd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. guaranteed by characterization results. table 43. main pll characteristics (continued) symbol parameter conditions min typ max unit table 44. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) 0.95 (2) 12.10mhz f plli2s_out plli2s multiplier output clock - - 216 mhz f vco_out plli2s vco output 100 - 432 mhz t lock plli2s lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps electrical characteristics stm32f437xx and stm32f439xx 126/240 docid024244 rev 10 i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. guaranteed by characterization results. table 44. plli2s (audio pll) characteristics (continued) symbol parameter conditions min typ max unit table 45. pllisai (audio and lcd-tft pll) characteristics symbol parameter conditions min typ max unit f pllsai_in pllsai input clock (1) 0.95 (2) 12.10mhz f pllsai_out pllsai multiplier ou tput clock - - 216 mhz f vco_out pllsai vco output 100 - 432 mhz t lock pllsai lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) main sai clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps fs clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(pllsai) (4) pllsai power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pllsai) (4) pllsai power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. guaranteed by characterization results. docid024244 rev 10 127/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.12 pll spread spec trum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 52: emi characteristics ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation dep th (modeper) is given by equation 1: equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generat ed because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: table 46. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - 2 15 ? 1- 1. guaranteed by design. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 == incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2.002%(peak) == electrical characteristics stm32f437xx and stm32f439xx 128/240 docid024244 rev 10 figure 33 and figure 34 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 33. pll output clock waveforms in center spread mode figure 34. pll output clock waveforms in down spread mode & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e x t m o d e m d a i m d ) u h t x h q f \ 3 / / b 2 8 7 7 l p h ) w p r g h [ w p r g h [ p g d l e docid024244 rev 10 129/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.13 memory characteristics flash memory the characteristics are given at ta = ?40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. table 47. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.7 v - 5 - ma write / erase 16-bit mode, v dd = 2.1 v - 8 - write / erase 32-bit mode, v dd = 3.3 v - 12 - table 48. flash memory programming symbol parameter conditions min (1) typ max (1) unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -1632 s program/erase parallelism (psize) = x 16 -1122 program/erase parallelism (psize) = x 32 -816 electrical characteristics stm32f437xx and stm32f439xx 130/240 docid024244 rev 10 t be bank erase time program/erase parallelism (psize) = x 8 -1632 s program/erase parallelism (psize) = x 16 -1122 program/erase parallelism (psize) = x 32 -816 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.7 - 3.6 v 1. guaranteed by characterization results. 2. the maximum programming time is m easured after 100k erase operations. table 49. flash memory programming with v pp symbol parameter conditions min (1) typ max (1) 1. guaranteed by design. unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v -16100 (2) 2. the maximum programming time is measured after 100k erase operations. s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 6.9 - s t be bank erase time - 6.9 - s v prog programming voltage 2.7 - 3.6 v v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (3) 3. v pp should only be connected during programming/erasing. cumulative time during which v pp is applied --1hour table 48. flash memory programming (continued) symbol parameter conditions min (1) typ max (1) unit docid024244 rev 10 131/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 50. flash memory endurance and data retention 6.3.14 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 51 . they are based on the ems levels and classes defined in application note an1709. when the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. the pins showing a middle range robustness are: pa0, pa1, pa2, ph2, ph3, ph4, ph5, pa3, pa 4, pa5, pa6, pa7, pc4, and pc5. as a consequence, it is recommended to add a serial resistor (1 k ? ) located as close as possible to the mcu to the pi ns exposed to noise (connected to tracks longer than 50 mm on pcb). symbol parameter conditions value unit min (1) 1. guaranteed by characterization results. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 51. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp176, t a =+25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 4a electrical characteristics stm32f437xx and stm32f439xx 132/240 docid024244 rev 10 designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc ? code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. table 52. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] max vs. [f hse /f cpu ] unit 25/168 mhz 25/180 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp176 package, conformi ng to sae j1752/3 eembc, art on, all peripheral clocks enabled, cl ock dithering disabled. 0.1 to 30 mhz 16 19 dbv 30 to 130 mhz 23 23 130 mhz to 1ghz 25 22 sae emi level 4 4 - v dd = 3.3 v, t a = 25 c, lqfp176 package, conformi ng to sae j1752/3 eembc, art on, all peripheral clocks enabled, cl ock dithering enabled 0.1 to 30 mhz 17 16 dbv 30 to 130 mhz 8 10 130 mhz to 1ghz 11 16 sae emi level 3.5 3.5 - docid024244 rev 10 133/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.15 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/esd a/jedec js-001 and ansi /esd s5.3.1 standards. static latchup two complementary static te sts are required on six pa rts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. table 53. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to ansi/esda/jedec js-001 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to ansi/esd s5.3.1, lqfp100/144/176, ufbga169/176, tfbga176 and wlcsp143 packages c3 250 t a = +25 c conforming to ansi/esd s5.3.1, lqfp208 package c3 250 1. guaranteed by characterization results. table 54. electric al sensitivities symbol parameter c onditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a electrical characteristics stm32f437xx and stm32f439xx 134/240 docid024244 rev 10 6.3.16 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induc ed leakage current on adjacent pins (out of ? 5 a/+0 a range), or other f unctional failure (for exampl e reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 55 . note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 55. i/o current injection susceptibility (1) symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 pin ? 0na ma injected current on nrst pin ? 0na injected current on pa0, pa1, pa2, pa3, pa6, pa7, pb0, pc0, pc1, pc2, pc3, pc4, pc 5, ph1, ph2, ph3, ph4, ph5 ? 0na injected current on tta pins: pa4 and pa5 ? 0+5 injected current on any other ft pin ? 5na 1. na = not applicable . docid024244 rev 10 135/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.17 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 56: i/o static characteristics are derived from tests performed under the conditions summarized in table 17 . all i/os are cmos and ttl compliant. table 56. i/o static characteristics symbol parameter conditions min typ max unit v il ft, tta and nrst i/o input low level voltage 1.7 v v dd 3.6 v - - 0.35v dd ? 0.04 (1) v 0.3v dd (2) boot0 i/o input low level voltage 1.75 v v dd 3.6 v, ? 40 c t a 105 c -- 0.1v dd +0.1 (1) 1.7 v v dd 3.6 v, 0c t a 105 c -- v ih ft, tta and nrst i/o input high level voltage (5) 1.7 v v dd 3.6 v 0.45v dd +0.3 (1) -- v 0.7v dd (2) boot0 i/o input high level voltage 1.75 v v dd 3.6 v, ? 40 c t a 105 c 0.17v dd +0.7 (1) -- 1.7 v v dd 3.6 v, 0c t a 105 c v hys ft, tta and nrst i/o input hysteresis 1.7 v v dd 3.6 v 10%v dd (3) -- v boot0 i/o input hysteresis 1.75 v v dd 3.6 v, ? 40 c t a 105 c 0.1 - - 1.7 v v dd 3.6 v, 0c t a 105 c i lkg i/o input leakage current (4) v ss v in v dd -- 1 a i/o ft input leakage current (5) v in = 5v - - 3 electrical characteristics stm32f437xx and stm32f439xx 136/240 docid024244 rev 10 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft i/os is shown in figure 35 . r pu weak pull-up equivalent resistor (6) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v ss 30 40 50 k pa10/pb12 (otg_fs_id, otg_hs_id) 71014 r pd weak pull- down equivalent resistor (7) all pins except for pa10/pb12 (otg_fs_id, otg_hs_id) v in = v dd 30 40 50 pa10/pb12 (otg_fs_id, otg_hs_id) 71014 c io (8) i/o pin capacitance - - 5 - pf 1. guaranteed by design. 2. tested in production. 3. with a minimum of 200 mv. 4. leakage could be higher than the maximum value, if nega tive current is injected on adjacent pins, refer to table 55: i/o current injection susceptibility 5. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors mu st be disabled. leakage could be higher than the maximum value, if negative current is injected on adjacent pins.refer to table 55: i/o current injection susceptibility 6. pull-up resistors are designed with a true resistance in seri es with a switchable pmos. th is pmos contribution to the series resistance is minimum (~10% order). 7. pull-down resistors are designed with a tr ue resistance in series with a switchabl e nmos. this nmos contribution to the series resistance is minimum (~10% order). 8. hysteresis voltage between schmitt trigger switch ing levels. guaranteed by characterization results. table 56. i/o static characteristics (continued) symbol parameter conditions min typ max unit docid024244 rev 10 137/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 35. ft i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14, pc15 and pi8 which can sink or source up to 3ma. when using the pc13 to pc15 and pi8 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 15 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 15 ). 0 6 9 9 ' ' 9 9 , / 9 , + 9 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q & 0 2 6 u h t x l u h p h q w 9 , / p d [ 9 ' ' % d v h g r q ' h v l j q v l p x o d w l r q v 9 , / p d [ 9 ' ' 7 7 / u h t x l u h p h q w 9 , + p l q 9 7 7 / u h t x l u h p h q w 9 , / p d [ 9 $ u h d q r w g h w h u p l q h g % d v h g r q ' h v l j q v l p x o d w l r q v 9 , + p l q 9 ' ' electrical characteristics stm32f437xx and stm32f439xx 138/240 docid024244 rev 10 output voltage levels unless otherwise specified, the parameters given in table 57 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . all i/os are cmos and ttl compliant. table 57. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximum rating specified in table 15 . and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 15 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin v dd ? 0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+ 8ma 2.7 v v dd 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1) output low level voltage for an i/o pin i io = +20 ma 2.7 v v dd 3.6 v -1.3 (4) 4. based on characterization data. v v oh (3) output high level voltage for an i/o pin v dd ? 1.3 (4) - v ol (1) output low level voltage for an i/o pin i io = +6 ma 1.8 v v dd 3.6 v -0.4 (4) v v oh (3) output high level voltage for an i/o pin v dd ? 0.4 (4) - v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.7 v v dd 3.6v -0.4 (5) 5. guaranteed by design. v v oh (3) output high level voltage for an i/o pin v dd ? 0.4 (5) - docid024244 rev 10 139/240 stm32f437xx and stm32f439xx electrical characteristics 198 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 36 and table 58 , respectively. unless otherwise specified, the parameters given in table 58 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 17 . table 58. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 4 mhz c l = 50 pf, v dd 1.7 v - - 2 c l = 10 pf, v dd 2.7 v - - 8 c l = 10 pf, v dd 1.8 v - - 4 c l = 10 pf, v dd 1.7 v - - 3 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.7 v to 3.6 v --100ns 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 25 mhz c l = 50 pf, v dd 1.8 v - - 12.5 c l = 50 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 2.7 v - - 50 c l = 10 pf, v dd 1.8 v - - 20 c l = 10 pf, v dd 1.7 v - - 12.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd 2.7 v - - 10 ns c l = 10 pf, v dd 2.7 v - - 6 c l = 50 pf, v dd 1.7 v - - 20 c l = 10 pf, v dd 1.7 v - - 10 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd 2.7 v - - 50 (4) mhz c l = 10 pf, v dd 2.7 v - - 100 (4) c l = 40 pf, v dd 1.7 v - - 25 c l = 10 pf, v dd 1.8 v - - 50 c l = 10 pf, v dd 1.7 v - - 42.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd 2.7 v - - 6 ns c l = 10 pf, v dd 2.7 v - - 4 c l = 40 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 1.7 v - - 6 electrical characteristics stm32f437xx and stm32f439xx 140/240 docid024244 rev 10 figure 36. i/o ac charac teristics definition 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd 2.7 v - - 100 (4) mhz c l = 30 pf, v dd 1.8 v - - 50 c l = 30 pf, v dd 1.7 v - - 42.5 c l = 10 pf, v dd 2.7 v - - 180 (4) c l = 10 pf, v dd 1.8 v - - 100 c l = 10 pf, v dd 1.7 v - - 72.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd 2.7 v - - 4 ns c l = 30 pf, v dd 1.8 v - - 6 c l = 30 pf, v dd 1.7 v - - 7 c l = 10 pf, v dd 2.7 v - - 2.5 c l = 10 pf, v dd 1.8 v - - 3.5 c l = 10 pf, v dd 1.7 v - - 4 - textipw pulse width of external signals detected by the exti controller -10--ns 1. guaranteed by design. 2. the i/o speed is configured using the o speedry[1:0] bits. refer to the stm32f4x x reference manual fo r a description of the gpiox_speedr gpio port output speed register. 3. the maximum frequency is defined in figure 36 . 4. for maximum frequencies above 50 mhz and v dd > 2.4 v, the compensation cell should be used. table 58. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w docid024244 rev 10 141/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.18 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 56: i/o static characteristics ). unless otherwise specified, the parameters given in table 59 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 17 . figure 37. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the external capacitor must be placed as close as possibl e to the device. 3. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 59 . otherwise the reset is not taken into account by the device. table 59. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in = v ss 30 40 50 k v f(nrst) (2) nrst input filtered pulse - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design. d l f 6 7 0 ) 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o 5 h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w electrical characteristics stm32f437xx and stm32f439xx 142/240 docid024244 rev 10 6.3.19 tim time r characteristics the parameters given in table 60 are guaranteed by design. refer to section 6.3.17: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 6.3.20 communications interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s. the i 2 c timings requirements are guaranteed by de sign when the i2c peripheral is properly configured (refer to rm0090 reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. refer to section 6.3.17: i/o po rt characteristics for more details on the i 2 c i/o characteristics . all i 2 c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 60. timx characteristics (1)(2) 1. timx is used as a general term to refer to the tim1 to tim12 timers. 2. guaranteed by design. symbol parameter conditions (3) 3. the maximum timer frequency on apb1 or apb2 is up to 180 mhz, by setting the timpre bit in the rcc_dckcfgr register, if apbx prescaler is 1 or 2 or 4, then timxclk = hckl, otherwise timxclk = 4x pclkx. min max unit t res(tim) timer resolution time ahb/apbx prescaler=1 or 2 or 4, f timxclk = 180 mhz 1- t timxclk ahb/apbx prescaler>4, f timxclk = 90 mhz 1- t timxclk f ext timer external clock frequency on ch1 to ch4 f timxclk = 180 mhz 0 f timxclk /2 mhz res tim timer resolution - 16/32 bit t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk docid024244 rev 10 143/240 stm32f437xx and stm32f439xx electrical characteristics 198 spi interface characteristics unless otherwise specified, the parameters given in table 62 for the spi interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 61. i2c analog filter characteristics (1) 1. guaranteed by design. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns table 62. spi dynamic characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode, spi1/4/5/6, 2.7 v v dd 3.6 v -- 45 mhz slave mode, spi1/4/5/6, 2.7 v v dd 3.6 v receiver 45 transmitter/ full-duplex 38 (2) master mode, spi1/2/3/4/5/6, 1.7 v v dd 3.6 v -- 22.5 slave mode, spi1/2/3/4/5/6, 1.7 v v dd 3.6 v 22.5 duty(sck) duty cycle of spi clock frequency slave mode 30 50 70 % electrical characteristics stm32f437xx and stm32f439xx 144/240 docid024244 rev 10 t w(sckh) sck high and low time master mode, spi presc = 2, 2.7 v v dd 3.6 v t pclk ? 0.5 t pclk t pclk +0.5 ns t w(sckl) master mode, spi presc = 2, 1.7 v v dd 3.6 v t pclk ? 2 t pclk t pclk +2 t su(nss) nss setup time slave mode, spi presc = 2 4 t pclk -- t h(nss) nss hold time slave mode, spi presc = 2 2 t pclk t su(mi) data input setup time master mode 3 - - t su(si) slave mode 0 - - t h(mi) data input hold time master mode 0.5 - - t h(si) slave mode 2 - - t a(so ) data output access time slave mode, spi presc = 2 0 - 4 t pclk t dis(so) data output disable time slave mode, spi1/4/5/6, 2.7 v v dd 3.6 v 0-8.5 slave mode, spi1/2/3/4/5/6 and 1.7 v v dd 3.6 v 0-16.5 t v(so) t h(so) data output valid/hold time slave mode (after enable edge), spi1/4/5/6 and 2.7v v dd 3.6v -1113 ns slave mode (after enable edge), spi2/3, 2.7 v v dd 3.6 v -1415 slave mode (after enable edge), spi1/4/5/6, 1.7 v v dd 3.6 v -15.519 slave mode (after enable edge), spi2/3, 1.7 v v dd 3.6 v - 15.5 17.5 t v(mo) data output valid time master mode (after enable edge), spi1/4/5/6, 2.7 v v dd 3.6 v --2.5 master mode (after enable edge), spi1/2/3/4/5/6, 1.7 v v dd 3.6 v --4.5 t h(mo) data output hold time master mode (after enable edge) 0 - - 1. guaranteed by characterization results. 2. maximum frequency in slave transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value ca n be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50% table 62. spi dynamic characteristics (1) (continued) symbol parameter conditions min typ max unit docid024244 rev 10 145/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 38. spi timing diagram - slave mode and cpha = 0 figure 39. spi timing diagram - slave mode and cpha = 1 d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 electrical characteristics stm32f437xx and stm32f439xx 146/240 docid024244 rev 10 figure 40. spi timing diagram - master mode d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 docid024244 rev 10 147/240 stm32f437xx and stm32f439xx electrical characteristics 198 i 2 s interface characteristics unless otherwise specified, the parameters given in table 63 for the i 2 s interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (ck, sd, ws). note: refer to the i2s section of rm0090 reference manual for more details on the sampling frequency (f s ). f mck , f ck , and d ck values reflect only the digital peripheral behavior. the values of these parameters might be slightly impacted by the source clock precision. d ck depends mainly on the value of odd bit. the digital contribution leads to a minimum value of (i2sdiv/(2*i2sdiv+odd) and a maximum va lue of (i2sdiv+odd) /(2*i2sdiv+odd). f s maximum value is supported for each mode/condition. table 63. i 2 s dynamic characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256x8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode 0 6 ns t h(ws) ws hold time master mode 0 - t su(ws) ws setup time slave mode 1 - t h(ws) ws hold time slave mode 0 - t su(sd_mr) data input setup time master receiver 7.5 - t su(sd_sr) slave receiver 2 - t h(sd_mr) data input hold time master receiver 0 - t h(sd_sr) slave receiver 0 - t v(sd_st) t h(sd_st) data output valid time slave transmitter (after enable edge) - 27 t v(sd_mt) master transmitter (after enable edge) - 20 t h(sd_mt) data output hold time master tran smitter (after enable edge) 2.5 - 1. guaranteed by characterization results. 2. the maximum value of 256xfs is 45 mhz (apb1 maximum frequency). electrical characteristics stm32f437xx and stm32f439xx 148/240 docid024244 rev 10 figure 41. i 2 s slave timing diagram (philips protocol) (1) 1. .lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 42. i 2 s master timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t docid024244 rev 10 149/240 stm32f437xx and stm32f439xx electrical characteristics 198 sai characteristics unless otherwise specified, the parameters given in table 64 for sai are derived from tests performed under the ambient temperature, f pclkx frequency and vdd supply voltage conditions su mmarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c=30 pf ? measurement points are performed at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (sck,sd,ws). table 64. sai characteristics (1) symbol parameter conditions min max unit f mckl sai main clock output - 256 x 8k 256xfs (2) mhz f sck sai clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d sck sai clock frequency duty cycle slave receiver 30 70 % t v(fs) fs valid time master mode 8 22 ns t su(fs) fs setup time slave mode 2 - t h(fs) fs hold time master mode 8 - slave mode 0 - t su(sd_mr) data input setup time master receiver 5 - t su(sd_sr) slave receiver 3 - t h(sd_mr) data input hold time master receiver 0 - t h(sd_sr) slave receiver 0 - t v(sd_st) t h(sd_st) data output valid time slave transmitter (after enable edge) -22 t v(sd_mt) master transmitter (after enable edge) -20 t h(sd_mt) data output hold time master transmitter (after enable edge) 8- 1. guaranteed by characterization results. 2. 256xfs maximum corresponds to 45 mhz (apb2 xaximum frequency) electrical characteristics stm32f437xx and stm32f439xx 150/240 docid024244 rev 10 figure 43. sai master timing waveforms figure 44. sai slave timing waveforms - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 o u t p u t f 3 # + 3 ! ) ? 3 $ ? 8 t r a n s m i t t v & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t h & 3 3 l o t n t v 3 $ ? - 4 t h 3 $ ? - 4 3 l o t n t s u 3 $ ? - 2 t h 3 $ ? - 2 - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 i n p u t 3 ! ) ? 3 $ ? 8 t r a n s m i t t s u & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t w # + ( ? 8 t h & 3 3 l o t n t v 3 $ ? 3 4 t h 3 $ ? 3 4 3 l o t n t s u 3 $ ? 3 2 t w # + , ? 8 t h 3 $ ? 3 2 f 3 # + docid024244 rev 10 151/240 stm32f437xx and stm32f439xx electrical characteristics 198 usb otg full speed (fs) characteristics this interface is present in both the usb otg hs and usb otg fs controllers. note: when vbus sensing feature is enabled, pa9 and pb13 should be left at their default state (floating input), not as alternate function. a typical 200 a current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on pa9 and pb13 when the feature is enabled. table 65. usb otg full speed startup time symbol parameter max unit t startup (1) 1. guaranteed by design. usb otg full speed transceiver startup time 1 s table 66. usb otg full speed dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg full speed transceiver operating voltage 3.0 (2) 2. the usb otg full speed transceiver functionality is ensured down to 2.7 v but not the full usb full speed electrical charac teristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg full speed drivers. --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55 electrical characteristics stm32f437xx and stm32f439xx 152/240 docid024244 rev 10 figure 45. usb otg full speed timings: definition of data signal rise and fall time usb high speed (hs) characteristics unless otherwise specified, the parameters given in table 70 for ulpi are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 69 and v dd supply voltage cond itions summarized in table 68 , with the following configuration: ? output speed is set to ospeedry[1 :0] = 10, unless ot herwise specified ? capacitive load c = 30 pf, unless otherwise specified ? measurement points are done at cmos levels: 0.5v dd . refer to section 6.3.17: i/o port characteristics for more details on the input/output characteristics. table 67. usb otg full speed electrical characteristics (1) 1. guaranteed by design. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal cro ssover voltage 1.3 2.0 v z drv output driver impedance (3) 3. no external termination series resistors are requ ired on dp (d+) and dm (d-) pins since the matching impedance is included in the embedded driver. driving high or low 28 44 table 68. usb hs dc elect rical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd usb otg hs operating voltage 1.7 3.6 v d l e & u r v v r y h u s r l q w v ' l i i h u h q w l d o g d w d o l q h v 9 & 5 6 9 6 6 w i w u docid024244 rev 10 153/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 46. ulpi timing diagram table 69. usb hs cloc k timing parameters (1) 1. guaranteed by design. symbol parameter min typ max unit f hclk value to guarantee proper operation of usb hs interface 30 - - mhz f start_8bit frequency (first transition) 8-bit 10% 54 60 66 mhz f steady frequency (steady state) 500 ppm 59.97 60 60.03 mhz d start_8bit duty cycle (first transition) 8-bit 10% 40 50 60 % d steady duty cycle (steady state) 500 ppm 49.975 50 50.025 % t steady time to reach the steady state frequency and duty cycle after the first transition --1.4ms t start_dev clock startup time after the de-assertion of suspendm peripheral - - 5.6 ms t start_host host - - - t prep phy preparation time after the first transition of the input clock ---s # l o c k # o n t r o l ) n 5 , 0 ) ? $ ) 2 5 , 0 ) ? . 8 4 d a t a ) n b i t # o n t r o l o u t 5 , 0 ) ? 3 4 0 d a t a o u t b i t t $ $ t $ # t ( $ t 3 $ t ( # t 3 # a i c t $ # electrical characteristics stm32f437xx and stm32f439xx 154/240 docid024244 rev 10 table 70. dynamic characteristics: usb ulpi (1) symbol parameter conditions min. typ. max. unit t sc control in (ulpi_dir, ulpi_nxt) setup time 2 - - ns t hc control in (ulpi_dir, ulpi_nxt) hold time 0.5 - - t sd data in setup time 1.5 - - t hd data in hold time 2 - - t dc /t dd data/control output delay 2.7 v < v dd < 3.6 v, c l = 15 pf and ospeedry[1:0] = 11 -99.5 2.7 v < v dd < 3.6 v, c l = 20 pf and ospeedry[1:0] = 10 - 12 15 1.7 v < v dd < 3.6 v, c l = 15 pf and ospeedry[1:0] = 11 - 1. guaranteed by characterization results. docid024244 rev 10 155/240 stm32f437xx and stm32f439xx electrical characteristics 198 ethernet characteristics unless otherwise specified, the parameters given in table 71 , table 72 and table 73 for smi, rmii and mii are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 17 with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf for 2.7 v < v dd < 3.6 v ? capacitive load c = 20 pf for 1.71 v < v dd < 3.6 v ? measurement points are done at cmos levels: 0.5v dd . refer to section 6.3.17: i/o port characteristics for more details on the input/output characteristics. table 71 gives the list of ethernet mac signals for the smi (station management interface) and figure 47 shows the corresponding timing diagram. figure 47. ethernet smi timing diagram table 71. dynamics characteristics: ethernet mac signals for smi (1) 1. guaranteed by characterization results. symbol parameter min typ max unit t mdc mdc cycle time(2.38 mhz) 411 420 425 ns t d(mdio) write data valid time 6 10 13 t su(mdio) read data setup time 12 - - t h(mdio) read data hold time 0 - - 0 6 9 ( 7 + b 0 ' & ( 7 + b 0 ' , 2 2 ( 7 + b 0 ' , 2 , w 0 ' & w g 0 ' , 2 w v x 0 ' , 2 w k 0 ' , 2 electrical characteristics stm32f437xx and stm32f439xx 156/240 docid024244 rev 10 table 72 gives the list of ethernet mac signals for the rmii and figure 48 shows the corresponding timing diagram. figure 48. ethernet rmii timing diagram table 73 gives the list of ethernet mac signals for mii and figure 48 shows the corresponding timing diagram. d l e 5 0 , , b 5 ( ) b & / . 5 0 , , b 7 ; b ( 1 5 0 , , b 7 ; ' > @ 5 0 , , b 5 ; ' > @ 5 0 , , b & 5 6 b ' 9 w g 7 ; ( 1 w g 7 ; ' w v x 5 ; ' w v x & 5 6 w l k 5 ; ' w l k & 5 6 table 72. dynamics characteristics: ethernet mac signals for rmii (1) symbol parameter condition min typ max unit t su(rxd) receive data setup time 1.71 v < v dd < 3.6 v 1.5 - - ns t ih(rxd) receive data hold time 0 - - t su(crs) carrier sense setup time 1 - - t ih(crs) carrier sense hold time 1 - - t d(txen) transmit enable valid delay time 2.7 v < v dd < 3.6 v 8 10.5 12 1.71 v < v dd < 3.6 v 8 10.5 14 t d(txd) transmit data valid delay time 2.7 v < v dd < 3.6 v 8 11 12.5 1.71 v < v dd < 3.6 v 8 11 14.5 1. guaranteed by characterization results. docid024244 rev 10 157/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 49. ethernet mii timing diagram can (controller area network) interface refer to section 6.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (canx_tx and canx_rx). a i b 0 , , b 5 ; b & / . 0 , , b 5 ; ' > @ 0 , , b 5 ; b ' 9 0 , , b 5 ; b ( 5 w g 7 ; ( 1 w g 7 ; ' w v x 5 ; ' w v x ( 5 w v x ' 9 w l k 5 ; ' w l k ( 5 w l k ' 9 0 , , b 7 ; b & / . 0 , , b 7 ; b ( 1 0 , , b 7 ; ' > @ table 73. dynamics characteristics: ethernet mac signals for mii (1) symbol parameter condition min typ max unit t su(rxd) receive data setup time 1.71 v < v dd < 3.6 v 9-- ns t ih(rxd) receive data hold time 10 - - t su(dv) data valid setup time 9 - - t ih(dv) data valid hold time 8 - - t su(er) error setup time 6 - - t ih(er) error hold time 8 - - t d(txen) transmit enable valid delay time 2.7 v < v dd < 3.6 v 8 10 14 1.71 v < v dd < 3.6 v 8 10 16 t d(txd) transmit data valid delay time 2.7 v < v dd < 3.6 v 7.5 10 15 1.71 v < v dd < 3.6 v 7.5 10 17 1. guaranteed by characterization results. electrical characteristics stm32f437xx and stm32f439xx 158/240 docid024244 rev 10 6.3.21 12-bit adc characteristics unless otherwise specified, the parameters given in table 74 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 17 . table 74. adc characteristics symbol parameter conditions min typ max unit v dda power supply v dda ? v ref+ < 1.2 v 1.7 (1) -3.6 v v ref+ positive reference voltage 1.7 (1) -v dda v ref- negative reference voltage - - 0 - f adc adc clock frequency v dda = 1.7 (1) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v 0.6 30 36 mhz f trig (2) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz - - 17 1/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 for details --50k r adc (2)(4) sampling switch resistance - - 6 k c adc (2) internal sample and hold capacitor -47pf t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s 3-4801/f adc t stab (2) power-up time - 2 3 s t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.30 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc docid024244 rev 10 159/240 stm32f437xx and stm32f439xx electrical characteristics 198 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. f s (2) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode - - 6 msps i vref+ (2) adc v ref dc current consumption in conversion mode -300500a i vdda (2) adc v dda dc current consumption in conversion mode -1.61.8ma 1. v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.17.2: internal reset off ). 2. guaranteed by characterization results. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.7 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 74 . table 74. adc characteristics (continued) symbol parameter conditions min typ max unit table 75. adc static accuracy at f adc = 18 mhz symbol parameter test conditions typ max (1) 1. guaranteed by characterization results. unit et total unadjusted error f adc =18 mhz v dda = 1.7 to 3.6 v v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 3 4 lsb eo offset error 2 3 eg gain error 1 3 ed differential linearity error 1 2 el integral linearity error 2 3 r ain k0.5 ? () f adc c adc 2 n 2 + () ln ---------------------------------------------------------------- r adc ? = electrical characteristics stm32f437xx and stm32f439xx 160/240 docid024244 rev 10 a table 76. adc static accuracy at f adc = 30 mhz symbol parameter test conditions typ max (1) unit et total unadjusted error f adc = 30 mhz, r ain < 10 k , v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v, v dda ? v ref < 1.2 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 1. guaranteed by characterization results. table 77. adc static accuracy at f adc = 36 mhz symbol parameter test conditions typ max (1) unit et total unadjusted error f adc =36 mhz, v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 4 7 lsb eo offset error 2 3 eg gain error 3 6 ed differential linearity error 2 3 el integral linearity error 3 6 1. guaranteed by characterization results. table 78. adc dynamic accuracy at f adc = 18 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =18 mhz v dda = v ref+ = 1.7 v input frequency = 20 khz temperature = 25 c 10.3 10.4 - bits sinad signal-to-noise and distortion ratio 64 64.2 - db snr signal-to-noise ratio 64 65 - thd total harmonic distortion ? 67 ? 72 - 1. guaranteed by characterization results. table 79. adc dynamic accuracy at f adc = 36 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =36 mhz v dda = v ref+ = 3.3 v input frequency = 20 khz temperature = 25 c 10.6 10.8 - bits sinad signal-to noise and distortion ratio 66 67 - db snr signal-to noise ratio 64 68 - thd total harmonic distortion ? 70 ? 72 - 1. guaranteed by characterization results. docid024244 rev 10 161/240 stm32f437xx and stm32f439xx electrical characteristics 198 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.17 does not affect the adc accuracy. figure 50. adc accuracy characteristics 1. see also table 76 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. a i c % / % ' , 3 " ) $ % ! , % 4 % $ % , 6 $ $ ! 6 3 3 ! 6 2 % & o r d e p e n d i n g o n p a c k a g e = 6 $ $ ! ; , 3 " ) $ % ! , electrical characteristics stm32f437xx and stm32f439xx 162/240 docid024244 rev 10 figure 51. typical connecti on diagram using the adc 1. refer to table 74 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. d l 6 7 0 ) 9 ' ' $ , 1 [ , / ? ? $ 9 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 9 7 5 $ ' & & $ ' & e l w f r q y h u w h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u docid024244 rev 10 163/240 stm32f437xx and stm32f439xx electrical characteristics 198 general pcb design guidelines power supply decoupling should be performed as shown in figure 52 or figure 53 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 52. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . 6 7 0 ) ? ) q ) ? ) q ) 9 5 ( ) 9 ' ' $ 9 6 6 $ 9 5 ( ) d l e electrical characteristics stm32f437xx and stm32f439xx 164/240 docid024244 rev 10 figure 53. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . 6.3.22 temperature sensor characteristics 6 7 0 ) ? ) q ) d l f 9 5 ( ) 9 ' ' $ 9 5 ( ) 9 6 6 $ table 80. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 mv/c v 25 (1) voltage at 25 c - 0.76 v t start (2) startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. guaranteed by characterization results. 2. guaranteed by design. table 81. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff 7a2c - 0x1fff 7a2d ts_cal2 ts adc raw data acquired at temperature of 110 c, v dda = 3.3 v 0x1fff 7a2e - 0x1fff 7a2f docid024244 rev 10 165/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.23 v bat monitoring characteristics 6.3.24 reference voltage the parameters given in table 83 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . table 82. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 4 - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design. 2. shortest sampling time can be determined in the application by multiple iterations. table 83. internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage 10 - - s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3v 10mv - 3 5 mv t coeff (2) temperature coefficient - 30 50 ppm/c t start (2) startup time - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design, not tested in production table 84. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c vdda = 3.3 v 0x1fff 7a2a - 0x1fff 7a2b electrical characteristics stm32f437xx and stm32f439xx 166/240 docid024244 rev 10 6.3.25 dac electri cal characteristics table 85. dac characteristics symbol parameter conditions min typ max unit comments v dda analog supply voltage - 1.7 (1) -3.6 v- v ref+ reference supply voltage -1.7 (1) -3.6vv ref+ v dda v ssa ground - 0 - 0 v - r load (2) resistive load dac output buffer on r load connected to v ssa 5- - k - r load connected to v dda 25 - r o (2) impedance output with buffer off ---15k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_o ut min (2) lower dac_out voltage with buffer on -0.2 --v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.7 v dac_o ut max (2) higher dac_out voltage with buffer on --- v dda ? 0.2 v dac_o ut min (2) lower dac_out voltage with buffer off --0.5-mv it gives the maximum output excursion of the dac. dac_o ut max (2) higher dac_out voltage with buffer off --- v ref+ ? 1lsb v i vref+ (4) dac dc v ref current consumption in quiescent mode (standby mode) - - 170 240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs - - 50 75 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs docid024244 rev 10 167/240 stm32f437xx and stm32f439xx electrical characteristics 198 i dda (4) dac dc vdda current consumption in quiescent mode (3) - - 280 380 a with no load, middle code (0x800) on the inputs - - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (4) differential non linearity difference between two consecutive code- 1lsb) - - - 0.5 lsb given for the dac in 10-bit configuration. ---2 lsb given for the dac in 12-bit configuration. inl (4) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) ---1lsb given for the dac in 10-bit configuration. ---4lsb given for the dac in 12-bit configuration. offset (4) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) ---10mv given for the dac in 12-bit configuration ---3lsb given for the dac in 10-bit at v ref+ = 3.6 v ---12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (4) gain error - - - 0.5 % given for the dac in 12-bit configuration t settlin g (4) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb --36s c load 50 pf, r load 5 k thd (4) total harmonic distortion buffer on ----db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) ---1 ms/ s c load 50 pf, r load 5 k table 85. dac characteristics (continued) symbol parameter conditions min typ max unit comments electrical characteristics stm32f437xx and stm32f439xx 168/240 docid024244 rev 10 figure 54. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. t wakeup ( 4) wakeup time from off state (setting the enx bit in the dac control register) --6.510s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - - ?67 ?40 db no r load , c load = 50 pf 1. v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 3.17.2: internal reset off ). 2. guaranteed by design. 3. the quiescent mode corresponds to a state where the dac ma intains a stable output level to ensure that no dynamic consumption occurs. 4. guaranteed by characterization. table 85. dac characteristics (continued) symbol parameter conditions min typ max unit comments d l d % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u % x i i h u h g q r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 5 / 2 $ ' & / 2 $ ' docid024244 rev 10 169/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.26 fmc characteristics unless otherwise specified, the parameters given in table 86 to table 101 for the fmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeed ry[1:0] = 10 except at v dd range 1.7 to 2.1v where ospeedry[1:0] = 11 ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output characteristics. asynchronous waveforms and timings figure 55 through figure 58 represent asynchronous waveforms and table 86 through table 93 provide the corresponding ti mings. the results shown in these tables are obtained with the following fm c configuration: ? addresssetuptime = 0x1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 (except for asynchronous nwait mode , datasetuptime = 0x5) ? busturnaroundduration = 0x0 ? for sdram memories, v dd ranges from 2.7 to 3.6 v and maximum frequency fmc_sdclk = 90 mhz ? for mobile lpsdr sdram memories, v dd ranges from 1.7 to 1.95 v and maximum frequency fmc_sdclk = 84 mhz electrical characteristics stm32f437xx and stm32f439xx 170/240 docid024244 rev 10 figure 55. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. table 86. asynchronous non-multiplexed sram/psram/nor - read timings (1)(2) symbol parameter min max unit t w(ne) fmc_ne low time 2t hclk ? 0.5 2 t hclk +0.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 0 1 ns t w(noe) fmc_noe low time 2t hclk 2t hclk + 0.5 ns t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - ns t v(a_ne) fmc_nex low to fmc_a valid - 2 ns t h(a_noe) address hold time after fmc_noe high 0 - ns t v(bl_ne) fmc_nex low to fmc_bl valid - 2 ns t h(bl_noe) fmc_bl hold time after fmc_noe high 0 - ns t su(data_ne) data to fmc_nex high setup time t hclk + 2.5 - ns t su(data_noe) data to fmc_noex high setup time t hclk +2 - ns $ a t a & - # ? . % & - # ? . " , ; = & - # ? $ ; = t v " , ? . % t h $ a t a ? . % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % & - # ? . 7 % t s u $ a t a ? . % t w . % - 3 6 w . / % t t v . / % ? . % t h . % ? . / % t h $ a t a ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 docid024244 rev 10 171/240 stm32f437xx and stm32f439xx electrical characteristics 198 t h(data_noe) data hold time after fmc_noe high 0 - ns t h(data_ne) data hold time after fmc_nex high 0 - ns t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 ns t w(nadv) fmc_nadv low time - t hclk +1 ns 1. c l = 30 pf. 2. guaranteed by characterization results. table 87. asynchronous non-multiplexed sram/psram/nor read - nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 7t hclk +0.5 7t hclk +1 ns t w(noe) fmc_nwe low time 5t hclk ? 1.5 5t hclk +2 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 - table 86. asynchronous non-multiplexed sram/psram/nor - read timings (1)(2) (continued) symbol parameter min max unit electrical characteristics stm32f437xx and stm32f439xx 172/240 docid024244 rev 10 figure 56. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. table 88. asynchronous non-multipl exed sram/psram/nor write timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk 3t hclk +1 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk ? 0.5 t hclk + 0.5 ns t w(nwe) fmc_nwe low time t hclk t hclk + 0.5 ns t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk +1.5 - ns t v(a_ne) fmc_nex low to fmc_a valid - 0 ns t h(a_nwe) address hold time after fmc_nwe high t hclk +0.5 - ns t v(bl_ne) fmc_nex low to fmc_bl valid - 1.5 ns t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk +0.5 - ns t v(data_ne) data to fmc_nex low to data valid - t hclk + 2 ns t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - ns t v(nadv_ne) fmc_nex low to fmc_nadv low - 0.5 ns t w(nadv) fmc_nadv low time - t hclk + 0.5 ns . " , $ a t a & - # ? . % x & - # ? . " , ; = & - # ? $ ; = t v " , ? . % t h $ a t a ? . 7 % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % t w . 7 % & - # ? . 7 % t v . 7 % ? . % t h . % ? . 7 % t h ! ? . 7 % t h " , ? . 7 % t v $ a t a ? . % t w . % - 3 6 & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 docid024244 rev 10 173/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 57. asynchronous multiplexed psram/nor read waveforms table 89. asynchronous non-multiplexed sram/psram/nor write - nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk +1 8t hclk +2 ns t w(nwe) fmc_nwe low time 6t hclk ? 16t hclk +2 ns t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk +1.5 - ns t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 ns . " , $ a t a & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . % ! d d r e s s & - # ? ! ; = t v ! ? . % & - # ? . 7 % t v ! ? . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t s u $ a t a ? . % t h ! $ ? . ! $ 6 & - # ? . % & - # ? . / % t w . % t w . / % t v . / % ? . % t h . % ? . / % t h ! ? . / % t h " , ? . / % t s u $ a t a ? . / % t h $ a t a ? . / % & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 electrical characteristics stm32f437xx and stm32f439xx 174/240 docid024244 rev 10 table 90. asynchronous multiplexed psram/nor read timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk ? 13t hclk +0.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 2t hclk ? 0.5 2t hclk ns t tw(noe) fmc_noe low time t hclk ? 1t hclk +1 ns t h(ne_noe) fmc_noe high to fmc_ne high hold time 1 - ns t v(a_ne) fmc_nex low to fmc_a valid - 2 ns t v(nadv_ne) fmc_nex low to fmc_nadv low 0 2 ns t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk +0.5 ns t h(ad_nadv) fmc_ad(address) valid hold time after fmc_nadv high) 0 -ns t h(a_noe) address hold time after fmc_noe high t hclk ? 0.5 - ns t h(bl_noe) fmc_bl time after fmc_noe high 0 - ns t v(bl_ne) fmc_nex low to fmc_bl valid - 2 ns t su(data_ne) data to fmc_nex high setup time t hclk +1.5 - ns t su(data_noe) data to fmc_noe high setup time t hclk +1 - ns t h(data_ne) data hold time after fmc_nex high 0 - ns t h(data_noe) data hold time after fmc_noe high 0 - ns table 91. asynchronous multiplexed psram/nor read-nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk +0.5 8t hclk +2 ns t w(noe) fmc_nwe low time 5t hclk ? 15t hclk +1.5 ns t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - ns t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 ns docid024244 rev 10 175/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 58. asynchronous multip lexed psram/nor write waveforms . " , $ a t a & - # ? . % x & - # ? . " , ; = & - # ? ! $ ; = t v " , ? . % t h $ a t a ? . 7 % & - # ? . / % ! d d r e s s & - # ? ! ; = t v ! ? . % t w . 7 % & - # ? . 7 % t v . 7 % ? . % t h . % ? . 7 % t h ! ? . 7 % t h " , ? . 7 % t v ! ? . % t w . % - 3 6 ! d d r e s s & - # ? . ! $ 6 t v . ! $ 6 ? . % t w . ! $ 6 t v $ a t a ? . ! $ 6 t h ! $ ? . ! $ 6 & - # ? . 7 ! ) 4 t s u . 7 ! ) 4 ? . % t h . % ? . 7 ! ) 4 table 92. asynchronous multiplexed psram/nor write timings (1)(2) symbol parameter min max unit t w(ne) fmc_ne low time 4t hclk 4t hclk +0.5 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk ? 1t hclk +0.5 ns t w(nwe) fmc_nwe low time 2t hclk 2t hclk +0.5 ns t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk -ns t v(a_ne) fmc_nex low to fmc_a valid - 0 ns t v(nadv_ne) fmc_nex low to fmc_nadv low 0.5 1 ns t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk + 0.5 ns t h(ad_nadv) fmc_ad(adress) valid hold time after fmc_nadv high) t hclk ? 2-ns t h(a_nwe) address hold time after fmc_nwe high t hclk -ns t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk ? 2-ns t v(bl_ne) fmc_nex low to fmc_bl valid - 2 ns t v(data_nadv) fmc_nadv high to data valid - t hclk +1.5 ns t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - ns 1. c l = 30 pf. 2. guaranteed by characterization results. electrical characteristics stm32f437xx and stm32f439xx 176/240 docid024244 rev 10 synchronous waveforms and timings figure 59 through figure 62 represent synchronous waveforms and table 94 through table 97 provide the corresponding ti mings. the results shown in these tables are obtained with the following fm c configuration: ? burstaccessmode = fmc_ burstaccessmode_enable; ? memorytype = fmc_memorytype_cram; ? writeburst = fmc_writeburst_enable; ? clkdivision = 1; (0 is not supported, se e the stm32f4xx reference manual : rm0090) ? datalatency = 1 for nor flash; datalatency = 0 for psram in all timing tables, the t hclk is the hclk clock period (with maximum fmc_clk = 90 mhz). table 93. asynchronous multiplexed psram/nor write-nwait timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 9t hclk 9t hclk +0.5 ns t w(nwe) fmc_nwe low time 7t hclk 7t hclk +2 ns t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk +1.5 - ns t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk ?1 - ns docid024244 rev 10 177/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 59. synchronous multiplexed nor/psram read timings table 94. synchronous multiplexed nor/psram read timings (1)(2) symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 0 ns t d(clkh_nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk -ns t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 ns t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - ns t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 ns t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - ns t d(clkl-noel) fmc_clk low to fmc_noe low - t hclk +0.5 ns t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk ? 0.5 - ns t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 0.5 ns t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - ns & - # ? # , + & - # ? . % x & - # ? . ! $ 6 & - # ? ! ; = & - # ? . / % & - # ? ! $ ; = ! $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + ( . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + ( ! ) 6 t d # , + , . / % , t d # , + ( . / % ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u ! $ 6 # , + ( t h # , + ( ! $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 electrical characteristics stm32f437xx and stm32f439xx 178/240 docid024244 rev 10 figure 60. synchronous multiplexed psram write timings t su(adv-clkh) fmc_a/d[15:0] valid data before fmc_clk high 5 -ns t h(clkh-adv) fmc_a/d[15:0] valid data after fmc_clk high 0 - ns t su(nwait-clkh) fmc_nwait valid before fmc_clk high 4 - ns t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 - ns 1. c l = 30 pf. 2. guaranteed by characterization results. table 94. synchronous multiple xed nor/psram read timings (1)(2) (continued) symbol parameter min max unit & - # ? # , + & - # ? . % x & - # ? . ! $ 6 & - # ? ! ; = & - # ? . 7 % & - # ? ! $ ; = ! $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y " 5 3 4 5 2 . t d # , + , . % x , t d # , + ( . % x ( t d # , + , . ! $ 6 , t d # , + , ! 6 t d # , + , . ! $ 6 ( t d # , + ( ! ) 6 t d # , + ( . 7 % ( t d # , + , . 7 % , t d # , + ( . " , ( t d # , + , ! $ 6 t d # , + , ! $ ) 6 t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 t d # , + , $ a t a & - # ? . " , docid024244 rev 10 179/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 95. synchronous multiplexed psram write timings (1)(2) 1. c l = 30 pf. 2. guaranteed by characterization results. symbol parameter min max unit t w(clk) fmc_clk period, vdd range= 2.7 to 3.6 v 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 1.5 ns t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk -ns t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 ns t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - ns t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 ns t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk -ns t d(clkl-nwel) fmc_clk low to fmc_nwe low - 0 ns t (clkh-nweh) fmc_clk high to fmc_nwe high t hclk ? 0.5 - ns t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 3 ns t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - ns t d(clkl-data) fmc_a/d[15:0] valid data after fmc_clk low - 3 ns t d(clkl-nbll) fmc_clk low to fmc_nbl low 0 - ns t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk ? 0.5 - ns t su(nwait-clkh) fmc_nwait valid before fmc_clk high 4 - ns t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 - ns electrical characteristics stm32f437xx and stm32f439xx 180/240 docid024244 rev 10 figure 61. synchronous non-multiplexed nor/psram read timings table 96. synchronous non-multipl exed nor/psram read timings (1)(2) symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 1 - ns t (clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 0.5 ns t d(clkh- nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk -ns t d(clkl- nadvl) fmc_clk low to fmc_nadv low - 0 ns t d(clkl- nadvh) fmc_clk low to fmc_nadv high 0 - ns t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 ns t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk ? 0.5 - ns t d(clkl-noel) fmc_clk low to fmc_noe low - t hclk +2 ns t d(clkh- noeh) fmc_clk high to fmc_noe high t hclk ? 0.5 - ns t su(dv-clkh) fmc_d[15:0] valid data before fmc_clk high 5 - ns & - # ? # , + & - # ? . % x & - # ? ! ; = & - # ? . / % & - # ? $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y t d # , + , . % x , t d # , + ( . % x ( t d # , + , ! 6 t d # , + ( ! ) 6 t d # , + , . / % , t d # , + ( . / % ( t s u $ 6 # , + ( t h # , + ( $ 6 t s u $ 6 # , + ( t h # , + ( $ 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 - 3 6 & - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( docid024244 rev 10 181/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 62. synchronous non-multi plexed psram write timings t h(clkh-dv) fmc_d[15:0] valid data after fmc_clk high 0 - ns t (nwait-clkh) fmc_nwait valid before fmc_clk high 4 t h(clkh- nwait) fmc_nwait valid after fmc_clk high 0 1. c l = 30 pf. 2. guaranteed by characterization results. table 97. synchronous non-multiplexed psram write timings (1)(2) symbol parameter min max unit t (clk) fmc_clk period 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 0.5 ns t (clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk -ns t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 ns t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - ns t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 0 ns table 96. synchronous non-mult iplexed nor/psram read timings (1)(2) (continued) symbol parameter min max unit - 3 6 & - # ? # , + & - # ? . % x & - # ? ! ; = & - # ? . 7 % & - # ? $ ; = $ $ & - # ? . 7 ! ) 4 7 ! ) 4 # & ' b 7 ! ) 4 0 / , b t w # , + t w # , + $ a t a l a t e n c y t d # , + , . % x , t d # , + ( . % x ( t d # , + , ! 6 t d # , + ( ! ) 6 t d # , + ( . 7 % ( t d # , + , . 7 % , t d # , + , $ a t a t s u . 7 ! ) 4 6 # , + ( t h # , + ( . 7 ! ) 4 6 & - # ? . ! $ 6 t d # , + , . ! $ 6 , t d # , + , . ! $ 6 ( t d # , + , $ a t a & - # ? . " , t d # , + ( . " , ( electrical characteristics stm32f437xx and stm32f439xx 182/240 docid024244 rev 10 pc card/compactflash controller waveforms and timings figure 63 through figure 68 represent synchronous waveforms, and table 98 and table 99 provide the corresponding timings. the results shown in this table are obtained with the following fmc configuration: ? com.fmc_setuptime = 0x04; ? com.fmc_waitsetuptime = 0x07; ? com.fmc_holdsetuptime = 0x04; ? com.fmc_hizsetuptime = 0x00; ? att.fmc_setuptime = 0x04; ? att.fmc_waitsetuptime = 0x07; ? att.fmc_holdsetuptime = 0x04; ? att.fmc_hizsetuptime = 0x00; ? io.fmc_setuptime = 0x04; ? io.fmc_waitsetuptime = 0x07; ? io.fmc_holdsetuptime = 0x04; ? io.fmc_hizsetuptime = 0x00; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - ns t d(clkl-nwel) fmc_clk low to fmc_nwe low - 0 ns t d(clkh-nweh) fmc_clk high to fmc_nwe high t hclk ? 0.5 - ns t d(clkl-data) fmc_d[15:0] valid data after fmc_clk low - 2.5 ns t d(clkl-nbll) fmc_clk low to fmc_nbl low 0 - ns t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk ? 0.5 - ns t su(nwait-clkh) fmc_nwait valid before fmc_clk high 4 t h(clkh-nwait) fmc_nwait valid after fmc_clk high 0 1. c l = 30 pf. 2. guaranteed by characterization results. table 97. synchronous non-multiplexed psram write timings (1)(2) (continued) symbol parameter min max unit docid024244 rev 10 183/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 63. pc card/compactflash controll er waveforms for common memory read access 1. fmc_nce4_2 remains high (inac tive during 8-bit access. figure 64. pc card/compactflash contro ller waveforms for co mmon memory write access & - # ? . 7 % t w . / % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . # % ? . / % t s u $ . / % t h . / % $ t v . # % x ! t d . 2 % ' . # % x t d . ) / 2 $ . # % x t h . # % x ! ) t h . # % x . 2 % ' t h . # % x . ) / 2 $ t h . # % x . ) / 7 2 - 3 6 - 3 6 t d . # % ? . 7 % t w . 7 % t h . 7 % $ t v . # % ? ! t d . 2 % ' . # % ? t d . ) / 2 $ . # % ? t h . # % ? ! ) - % - x ( ) : t v . 7 % $ t h . # % ? . 2 % ' t h . # % ? . ) / 2 $ t h . # % ? . ) / 7 2 & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . 7 % . # % ? t d $ . 7 % & - # ? . # % ? ( i g h electrical characteristics stm32f437xx and stm32f439xx 184/240 docid024244 rev 10 figure 65. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). - 3 6 t d . # % ? . / % t w . / % t s u $ . / % t h . / % $ t v . # % ? ! t h . # % ? ! ) t d . 2 % ' . # % ? t h . # % ? . 2 % ' & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . / % . # % ? ( i g h docid024244 rev 10 185/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 66. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hi-z). figure 67. pc card/compactflash controll er waveforms for i/o space read access - 3 6 t w . 7 % t v . # % ? ! t d . 2 % ' . # % ? t h . # % ? ! ) t h . # % ? . 2 % ' t v . 7 % $ & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ t d . 7 % . # % ? ( i g h t d . # % ? . 7 % - 3 6 t d . ) / 2 $ . # % ? t w . ) / 2 $ t s u $ . ) / 2 $ t d . ) / 2 $ $ t v . # % x ! t h . # % ? ! ) & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ electrical characteristics stm32f437xx and stm32f439xx 186/240 docid024244 rev 10 figure 68. pc card/compactflash controller waveforms for i/o space write access t d . # % ? . ) / 7 2 t w . ) / 7 2 t v . # % x ! t h . # % ? ! ) t h . ) / 7 2 $ ! 4 4 x ( ) : t v . ) / 7 2 $ - 3 6 & - # ? . 7 % & - # ? . / % & - # ? $ ; = & - # ? ! ; = & - # ? . # % ? & - # ? . # % ? & - # ? . 2 % ' & - # ? . ) / 7 2 & - # ? . ) / 2 $ table 98. switching characteristics fo r pc card/cf read and write cycles in attribute/common space (1)(2) symbol parameter min max unit t v(ncex-a) fmc_ncex low to fmc_ay valid - 0 ns t h(ncex_ai) fmc_ncex high to fmc_ax invalid 0 - ns t d(nreg-ncex) fmc_ncex low to fmc_nreg valid - 1 ns t h(ncex-nreg) fmc_ncex high to fmc_nreg invalid t hclk ? 2-ns t d(ncex-nwe) fmc_ncex low to fmc_nwe low - 5t hclk ns t w(nwe) fmc_nwe low width 8t hclk ? 0.5 8t hclk +0.5 ns t d(nwe_ncex) fmc_nwe high to fmc_ncex high 5t hclk +1 - ns t v(nwe-d) fmc_nwe low to fmc_d[15:0] valid - 0 ns t h(nwe-d) fmc_nwe high to fmc_d[15:0] invalid 9t hclk ? 0.5 - ns t d(d-nwe) fmc_d[15:0] valid before fmc_nwe high 13t hclk ? 3ns t d(ncex-noe) fmc_ncex low to fmc_noe low - 5t hclk ns t w(noe) fmc_noe low width 8 t hclk ? 0.5 8 t hclk +0.5 ns t d(noe_ncex) fmc_noe high to fmc_ncex high 5t hclk ? 1-ns t su (d-noe) fmc_d[15:0] valid data before fmc_noe high t hclk -ns t h(noe-d) fmc_noe high to fmc_d[15:0] invalid 0 - ns 1. c l = 30 pf. 2. guaranteed by characterization results. docid024244 rev 10 187/240 stm32f437xx and stm32f439xx electrical characteristics 198 nand controller waveforms and timings figure 69 through figure 72 represent synchronous waveforms, and table 100 and table 101 provide the corresponding timings. the results shown in this table are obtained with the following fm c configuration: ? com.fmc_setuptime = 0x01; ? com.fmc_waitsetuptime = 0x03; ? com.fmc_holdsetuptime = 0x02; ? com.fmc_hizsetuptime = 0x01; ? att.fmc_setuptime = 0x01; ? att.fmc_waitsetuptime = 0x03; ? att.fmc_holdsetuptime = 0x02; ? att.fmc_hizsetuptime = 0x01; ? bank = fmc_bank_nand; ? memorydatawidth = fmc_memorydatawidth_16b; ? ecc = fmc_ecc_enable; ? eccpagesize = fmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. table 99. switching characteristics fo r pc card/cf read and write cycles in i/o space (1)(2) symbol parameter min max unit tw(niowr) fmc_niowr low width 8t hclk ? 0.5 - ns tv(niowr-d) fmc_niowr low to fmc_d[15:0] valid - 0 ns th(niowr-d) fmc_niowr high to fmc_d[15:0] invalid 9t hclk ? 2-ns td(nce4_1-niowr) fmc_nce4_1 low to fmc_niowr valid - 5t hclk ns th(ncex-niowr) fmc_ncex high to fmc_niowr invalid 5t hclk -ns td(niord-ncex) fmc_ncex low to fmc_niord valid - 5t hclk ns th(ncex-niord) fmc_ncex high to fmc_niord) valid 6t hclk +2 - ns tw(niord) fmc_niord low width 8t hclk ? 0.5 8t hclk +0.5 ns tsu(d-niord) fmc_d[15:0] va lid before fmc_niord high t hclk -ns td(niord-d) fmc_d[15:0] valid after fmc_niord high 0 - ns 1. c l = 30 pf. 2. guaranteed by characterization results. electrical characteristics stm32f437xx and stm32f439xx 188/240 docid024244 rev 10 figure 69. nand controller waveforms for read access figure 70. nand controller waveforms for write access & - # ? . 7 % & - # ? . / % . 2 % & - # ? $ ; = t s u $ . / % t h . / % $ - 3 6 ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . / % t h . / % ! , % - 3 6 t h . 7 % $ t v . 7 % $ & - # ? . 7 % & - # ? . / % . 2 % & - # ? $ ; = ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . 7 % t h . 7 % ! , % docid024244 rev 10 189/240 stm32f437xx and stm32f439xx electrical characteristics 198 figure 71. nand controller waveforms for common memory read access figure 72. nand controller wavefo rms for common memory write access table 100. switching characteristics for nand flash read cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(n0e) fmc_noe low width 4t hclk ? 0.5 4t hclk +0.5 ns t su(d-noe) fmc_d[15-0] valid data before fmc_noe high 9 - ns t h(noe-d) fmc_d[15-0] valid data after fmc_noe high 0 - ns t d(ale-noe) fmc_ale valid before fmc_noe low - 3t hclk ? 0.5 ns t h(noe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 2- ns - 3 6 & - # ? . 7 % & - # ? . / % & - # ? $ ; = t w . / % t s u $ . / % t h . / % $ ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . / % t h . / % ! , % - 3 6 t w . 7 % t h . 7 % $ t v . 7 % $ & - # ? . 7 % & - # ? . / % & - # ? $ ; = t d $ . 7 % ! , % & - # ? ! # , % & - # ? ! & - # ? . # % x t d ! , % . / % t h . / % ! , % electrical characteristics stm32f437xx and stm32f439xx 190/240 docid024244 rev 10 sdram waveforms and timings figure 73. sdram read access waveforms (cl = 1) table 101. switching ch aracteristics for nand flash write cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(nwe) fmc_nwe low width 4t hclk 4t hclk +1 ns t v(nwe-d) fmc_nwe low to fmc_d[15-0] valid 0 - ns t h(nwe-d) fmc_nwe high to fmc_d[15-0] invalid 3t hclk ? 1-ns t d(d-nwe) fmc_d[15-0] valid before fmc_nwe high 5t hclk ? 3-ns t d(ale-nwe) fmc_ale valid before fmc_nwe low - 3t hclk ? 0.5 ns t h(nwe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 1-ns - 3 6 2 o w n # o l & - # ? 3 $ # , + & - # ? ! > @ & - # ? 3 $ . 2 ! 3 & - # ? 3 $ . # ! 3 & - # ? 3 $ . 7 % & - # ? $ ; = & - # ? 3 $ . % ; = t d 3 $ # , + , ? ! d d 2 t d 3 $ # , + , ? ! d d # t h 3 $ # , + , ? ! d d 2 t h 3 $ # , + , ? ! d d # t d 3 $ # , + , ? 3 . $ % t s u 3 $ # , + ( ? $ a t a t h 3 $ # , + ( ? $ a t a # o l # o l i # o l n $ a t a $ a t a i $ a t a n $ a t a t h 3 $ # , + , ? 3 . $ % t d 3 $ # , + , ? . 2 ! 3 t d 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . 2 ! 3 docid024244 rev 10 191/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 102. sdram read timings (1)(2) 1. cl = 30 pf on data and address lines. cl=15pf on fmc_sdclk . 2. guaranteed by characterization results. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t su(sdclkh _data) data input setup time 2 - t h(sdclkh_data) data input hold time 0 - t d(sdclkl_add) address valid time - 1.5 t d(sdclkl- sdne) chip select valid time - 0.5 t h(sdclkl_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 0.5 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t h(sdclkl_sdncas) sdncas hold time 0 - table 103. lpsdr sdram read timings (1)(2) 1. cl = 10 pf . 2. guaranteed by characterization results. symbol paramete r min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t su(sdclkh_data) data input setup time 2.5 - t h(sdclkh_data) data input hold time 0 - t d(sdclkl_add) address valid time - 1 t d(sdclkl_sdne) chip select valid time - 1 t h(sdclkl_sdne) chip select hold time 1 - t d(sdclkl_sdnras sdnras valid time - 1 t h(sdclkl_sdnras) sdnras hold time 1 - t d(sdclkl_sdncas) sdncas valid time - 1 t h(sdclkl_sdncas) sdncas hold time 1 - electrical characteristics stm32f437xx and stm32f439xx 192/240 docid024244 rev 10 figure 74. sdram write access waveforms - 3 6 2 o w n # o l & - # ? 3 $ # , + & - # ? ! > @ & - # ? 3 $ . 2 ! 3 & - # ? 3 $ . # ! 3 & - # ? 3 $ . 7 % & - # ? $ ; = & - # ? 3 $ . % ; = t d 3 $ # , + , ? ! d d 2 t d 3 $ # , + , ? ! d d # t h 3 $ # , + , ? ! d d 2 t h 3 $ # , + , ? ! d d # t d 3 $ # , + , ? 3 . $ % t d 3 $ # , + , ? $ a t a t h 3 $ # , + , ? $ a t a # o l # o l i # o l n $ a t a $ a t a i $ a t a n $ a t a t h 3 $ # , + , ? 3 . $ % t d 3 $ # , + , ? . 2 ! 3 t d 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . # ! 3 t h 3 $ # , + , ? . 2 ! 3 t d 3 $ # , + , ? . 7 % t h 3 $ # , + , ? . 7 % & - # ? . " , ; = t d 3 $ # , + , ? . " , docid024244 rev 10 193/240 stm32f437xx and stm32f439xx electrical characteristics 198 table 104. sdram write timings (1)(2) 1. cl = 30 pf on data and address lines. cl=15pf on fmc_sdclk . 2. guaranteed by characterization results. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t d(sdclkl _data ) data output valid time - 3.5 t h(sdclkl _data) data output hold time 0 - t d(sdclkl_add) address valid time - 1.5 t d(sdclkl_sdnwe) sdnwe valid time - 1 t h(sdclkl_sdnwe) sdnwe hold time 0 - t d(sdclkl_ sdne) chip select valid time - 0.5 t h(sdclkl-_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 2 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t d(sdclkl_sdncas) sdncas hold time 0 - t d(sdclkl_nbl) nbl valid time - 0.5 t h(sdclkl_nbl) nbloutput time 0 - table 105. lpsdr sdram write timings (1)(2) 1. cl = 10 pf . 2. guaranteed by characterization results. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t d(sdclkl _data ) data output valid time - 5 t h(sdclkl _data) data output hold time 2 - t d(sdclkl_add) address valid time - 2.8 t d(sdclkl-sdnwe) sdnwe valid time - 2 t h(sdclkl-sdnwe) sdnwe hold time 1 - t d(sdclkl- sdne) chip select valid time - 1.5 t h(sdclkl- sdne) chip select hold time 1 - t d(sdclkl-sdnras) sdnras valid time - 1.5 t h(sdclkl-sdnras) sdnras hold time 1.5 - t d(sdclkl-sdncas) sdncas valid time - 1.5 t d(sdclkl-sdncas) sdncas hold time 1.5 - t d(sdclkl_nbl) nbl valid time - 1.5 t h(sdclkl-nbl) nbl output time 1.5 - electrical characteristics stm32f437xx and stm32f439xx 194/240 docid024244 rev 10 6.3.27 camera interface (d cmi) timing specifications unless otherwise specified, the parameters given in table 106 for dcmi are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage summarized in table 17 , with the following configuration: ? dcmi_pixclk polarity: falling ? dcmi_vsync and dcmi_hsync polarity: high ? data formats: 14 bits figure 75. dcmi timing diagram table 106. dcmi characteristics symbol parameter min max unit frequency ratio dcmi_pixclk/f hclk -0.4 dcmi_pixclk pixel clock input - 54 mhz d pixel pixel clock input duty cycle 30 70 % t su(data) data input setup time 2 - ns t h(data) data input hold time 2.5 - t su(hsync) t su(vsync) dcmi_hsync/dcmi_vsync input setup time 0.5 - t h(hsync) t h(vsync) dcmi_hsync/dcmi_vsync input hold time 1 - 0 6 9 ' & 0 , b 3 , ; & / . w v x 9 6 < 1 & w v x + 6 < 1 & ' & 0 , b + 6 < 1 & ' & 0 , b 9 6 < 1 & ' $ 7 $ > @ ' & 0 , b 3 , ; & / . w k + 6 < 1 & w k + 6 < 1 & w v x ' $ 7 $ w k ' $ 7 $ docid024244 rev 10 195/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.28 lcd-tft controller (ltdc) characteristics unless otherwise specified, the parameters given in table 107 for lcd-tft are derived from tests performed under the ambient temperature, f hclk frequency and vdd supply voltage summarized in table 17 , with the following configuration: ? lcd_clk polarity: high ? lcd_de polarity : low ? lcd_vsync and lcd_hsync polarity: high ? pixel formats: 24 bits table 107. ltdc characteristics symbol paramete rminmaxunit f clk ltdc clock output frequency - 42 mhz d clk ltdc clock output duty cycle 45 55 % t w(clkh) t w(clkl) clock high time, low time tw(clk)/2 ? 0.5 tw(clk)/2+0.5 ns t v(data) data output valid time - 3.5 t h(data) data output hold time 1.5 - t v(hsync) hsync/vsync/de output valid time -2.5 t v(vsync) t v(de) t h(hsync) hsync/vsync/de output hold time 2- t h(vsync) th(de) electrical characteristics stm32f437xx and stm32f439xx 196/240 docid024244 rev 10 figure 76. lcd-tft horizontal timing diagram figure 77. lcd-tft vertical timing diagram 0 6 9 / & ' b & / . w y + 6 < 1 & / & ' b + 6 < 1 & / & ' b ' ( / & ' b 5 > @ / & ' b * > @ / & ' b % > @ w & / . / & ' b 9 6 < 1 & w y + 6 < 1 & w y ' ( w k ' ( 1 j y f m 1 j y f m w y ' $ 7 $ w k ' $ 7 $ 1 j y f m / + 6 < 1 & z l g w k + r u l ] r q w d o e d f n s r u f k $ f w l y h z l g w k + r u l ] r q w d o e d f n s r u f k 2 q h o l q h 0 6 9 / & ' b & / . w y 9 6 < 1 & / & ' b 5 > @ / & ' b * > @ / & ' b % > @ w & / . / & ' b 9 6 < 1 & w y 9 6 < 1 & - l i n e s d a t a 9 6 < 1 & z l g w k 9 h u w l f d o e d f n s r u f k $ f w l y h z l g w k 9 h u w l f d o e d f n s r u f k 2 q h i u d p h docid024244 rev 10 197/240 stm32f437xx and stm32f439xx electrical characteristics 198 6.3.29 sd/sdio mmc card host in terface (sdio) characteristics unless otherwise specified, the parameters given in table 108 for the sdio/mmc interface are derived from tests performed under the ambient temperature, f pclk2 frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 6.3.17: i/o port characteristics for more details on the input/output characteristics. figure 78. sdio high-speed mode figure 79. sd default mode t 7 # + ( # + $ # - $ o u t p u t $ # - $ i n p u t t # t 7 # + , t / 6 t / ( t ) 3 5 t ) ( t f t r a i a i # + $ # - $ o u t p u t t / 6 $ t / ( $ electrical characteristics stm32f437xx and stm32f439xx 198/240 docid024244 rev 10 6.3.30 rtc characteristics table 108. dynamic characteristics: sd / mmc characteristics (1)(2) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode 0 48 mhz - sdio_ck/fpclk2 frequency ratio - - 8/3 - t w(ckl) clock low time fpp =48 mhz 8.5 9 - ns t w(ckh) clock high time fpp =48 mhz 8.3 10 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs fpp =48 mhz 3.5 - - ns t ih input hold time hs fpp =48 mhz 0 - - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs fpp =48 mhz - 4.5 7 ns t oh output hold time hs fpp =48 mhz 3 - - cmd, d inputs (referenced to ck) in sd default mode tisud input ? setup ? time ? sd fpp =24 mhz 1.5 - - ns tihd input ? hold ? time ? sd fpp =24 mhz 0.5 - - cmd, d outputs (referenced to ck) in sd default mode tovd output ? valid ? default ? time ? sd fpp =24 mhz -4.56.5 ns tohd output ? hold ? default ? time ? sd fpp =24 mhz 3.5 - - 1. guaranteed by characterization results. 2. v dd = 2.7 to 3.6 v. table 109. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4- docid024244 rev 10 199/240 stm32f437xx and stm32f439xx package information 233 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp100 package information figure 80. lqfp100 -100-pin, 14 x 14 mm low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! package information stm32f437xx and stm32f439xx 200/240 docid024244 rev 10 table 110. lqpf100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. docid024244 rev 10 201/240 stm32f437xx and stm32f439xx package information 233 figure 81. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. a i c package information stm32f437xx and stm32f439xx 202/240 docid024244 rev 10 device marking for lqfp100 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 82. lqfp100 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 ' d w h f r g h \ h d u z h h n 3 l q l g h q w l i l h u 6 7 0 ) 9 , 7 5 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h < : : docid024244 rev 10 203/240 stm32f437xx and stm32f439xx package information 233 7.2 wlcsp143 package information figure 83. wlcsp143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. $ : ( b 0 ( b 9 h ) * h h % r w w r p y l h z % x p s v l g h h $ e d o o o r f d w l r q ' $ r u l h q w d w l r q u h i h u h q f h 7 r s y l h z : d i h u e d f n v l g h ' h w d l o $ $ $ 6 l g h y l h z $ ( ' h w d l o $ 5 r w d w h g ? % x p s 6 h d w l q j s o d q h e $ $ d d d f f f g g g = = ; < e e e h h h package information stm32f437xx and stm32f439xx 204/240 docid024244 rev 10 figure 84. wlcsp143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint table 111. wlcsp143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 0.155 0.175 0.195 - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating. - 0.025 - - 0.0010 - b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 4.486 4.521 4.556 0.1766 0.1780 0.1794 e 5.512 5.547 5.582 0.2170 0.2184 0.2198 e - 0.400 - - 0.0157 - e1 - 4.000 - - 0.1575 - e2 - 4.800 - - 0.1890 - f - 0.2605 - - 0.0103 - g - 0.3735 - - 0.0147 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 0 6 9 ' v p ' s d g docid024244 rev 10 205/240 stm32f437xx and stm32f439xx package information 233 device marking for wlcsp143 the following figure gives an example of topside marking orientation versus ball a 1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 85. wlcsp143 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 112. wlcsp143 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 dpad 260 m max. (circular) 220 m recommended dsm 300 m min. (for 260 m diameter pad) pcb pad design non-solder mask defined via underbump allowed. 0 6 y 9 ' d w h f r g h < h d u : h h n e d o o $ 6 7 ) = , < 3 u r g x f w l g h q w l i l f d w l r q < : : 5 5 h y l v l r q f r g h package information stm32f437xx and stm32f439xx 206/240 docid024244 rev 10 7.3 lqfp144 package information figure 86. lqfp144-144-pin, 20 x 20 mm low-profile quad flat package outline 1. drawing is not to scale. h , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 * $ 8 * ( 3 / $ 1 ( p p 6 ( $ 7 , 1 * 3 / $ 1 ( ' ' ' ( ( ( . f f f & & $ b 0 ( b 9 $ $ $ / / f e $ docid024244 rev 10 207/240 stm32f437xx and stm32f439xx package information 233 table 113. lqfp144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.2 00 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.689 - e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package information stm32f437xx and stm32f439xx 208/240 docid024244 rev 10 figure 87. lqpf144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. d l h docid024244 rev 10 209/240 stm32f437xx and stm32f439xx package information 233 device marking for lqfp144 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 88. lqfp144 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 ' d w h f r g h < h d u : h h n 3 l q 5 5 h y l v l r q f r g h ) = , 7 3 u r g x f w l g h q w l i l f d w l r q < : : package information stm32f437xx and stm32f439xx 210/240 docid024244 rev 10 7.4 lqfp176 package information figure 89. lqfp176 - 176-pin, 24 x 24 mm low-profile quad flat package outline 1. drawing is not to scale. 4 ? - % ? 6 ! ! e % ( % $ ( $ : $ : % b m m g a u g e p l a n e ! , , k c ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . 3 e a t i n g p l a n e # ! table 114. lqfp176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 23.900 - 24.100 0.9409 - 0.9488 hd 25.900 - 26.100 1.0197 - 1.0276 docid024244 rev 10 211/240 stm32f437xx and stm32f439xx package information 233 zd - 1.250 - - 0.0492 - e 23.900 - 24.100 0.9409 - 0.9488 he 25.900 - 26.100 1.0197 - 1.0276 ze - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - l (2) 0.450 - 0.750 0.0177 - 0.0295 l1 - 1.000 - - 0.0394 - k0 - 70 - 7 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. l dimension is measured at gauge pl ane at 0.25 mm above the seating plane. table 114. lqfp176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max package information stm32f437xx and stm32f439xx 212/240 docid024244 rev 10 figure 90. lqfp176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. 4 ? & 0 ? 6 docid024244 rev 10 213/240 stm32f437xx and stm32f439xx package information 233 device marking for lqfp176 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 91. lqfp176 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 : : < 3 l q l g h q w l i l h u 6 7 0 ) , , 7 5 ' d w h f r g h < h d u z h h n 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h package information stm32f437xx and stm32f439xx 214/240 docid024244 rev 10 7.5 lqfp208 package information figure 92. lqfp208 - 208-pin, 28 x 28 mm low-profile quad flat package outline 1. drawing is not to scale. ' ' ' ( ( ( h / * $ 8 * ( 3 / $ 1 ( p p e & 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 f / $ $ $ $ 6 ) @ . & @ 7 . docid024244 rev 10 215/240 stm32f437xx and stm32f439xx package information 233 table 115. lqfp208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 -- - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 29.800 30.000 30.200 1.1732 1.1811 1.1890 d1 27.800 28.000 28.200 1.0945 1.1024 1.1102 d3 - 25.500 - - 1.0039 - e 29.800 30.000 30.200 1.1732 1.1811 1.1890 e1 27.800 28.000 28.200 1.0945 1.1024 1.1102 e3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0 3.5 7.0 0 3.5 7.0 ccc - -0.080 - -0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. package information stm32f437xx and stm32f439xx 216/240 docid024244 rev 10 figure 93. lqfp208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. 8 + b ) 3 b 9 docid024244 rev 10 217/240 stm32f437xx and stm32f439xx package information 233 device marking for lqfp208 the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 94. lqfp208 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 : : < 3 l q l g h q w l i l h u 6 7 0 ) % , 7 ' d w h f r g h < h d u z h h n 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q 5 package information stm32f437xx and stm32f439xx 218/240 docid024244 rev 10 7.6 ufbga169 package information figure 95. ufbga169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not to scale. table 116. ufbga169 - 169-bal l 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.0020 0.0031 0.0043 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 a3 - 0.130 - - 0.0051 - a4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 6.950 7.000 7.050 0.2736 0.2756 0.2776 d1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e 6.950 7.000 7.050 0.2736 0.2756 0.2776 e1 5.950 6.000 6.050 0.2343 0.2362 0.2382 e - 0.500 - - 0.0197 - $ < 9 b 0 ( b 9 6 h d w l q j s o d q h $ $ $ h ) ) h 1 $ % 2 7 7 2 0 9 , ( : ( ' 7 2 3 9 , ( : ? e e d o o v < ; < h h h ? 0 i i i ? 0 = = ; $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d e ' ( $ $ = = g g g 6 , ' ( 9 , ( : docid024244 rev 10 219/240 stm32f437xx and stm32f439xx package information 233 figure 96. ufbga169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint note: non-solder mask defined (nsmd) pads are recommended. 4 to 6 mils solder paste screen printing process. f 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted fr om mm and rounded to 4 decimal digits. table 117. ufbga169 recommended pc b design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 dpad 0.27 mm dsm 0.35 mm typ. (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter. table 116. ufbga169 - 169-bal l 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 0 6 9 ' v p ' s d g package information stm32f437xx and stm32f439xx 220/240 docid024244 rev 10 device marking for ufbga169 the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 97. ufbga169 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q % d o o $ l g h q w l i l h u ' d w h f r g h < h d u z h h n < : : 5 6 7 0 ) $ , + docid024244 rev 10 221/240 stm32f437xx and stm32f439xx package information 233 7.7 ufbga176+25 package information figure 98. ufbga176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline 1. drawing is not to scale. table 118. ufbga176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 0.600 - - 0.0236 a1 - - 0.110 - - 0.0043 a2 - 0.130 - - 0.0051 - a3 - 0.450 - - 0.0177 - a4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 d 9.850 10.000 10.150 0.3878 0.3937 0.3996 d1 - 9.100 - - 0.3583 - e 9.850 10.000 10.150 0.3878 0.3937 0.3996 e1 - 9.100 - - 0.3583 - e - 0.650 - - 0.0256 - z - 0.450 - - 0.0177 - ddd - - 0.080 - - 0.0031 $ ( b 0 ( b 9 ' ^ ?]vp ?ov ? z ? k d d k d s / t d k w s / t ? e e d o o v $ h h h ? 0 i i i ? 0 & & $ & $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d e ( $ package information stm32f437xx and stm32f439xx 222/240 docid024244 rev 10 figure 99. ufbga176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 119. ufbga176+25 recommended pcb design rules (0.65 mm pitch bga) dimension recommended values pitch 0.65 mm dpad 0.300 mm dsm 0.400 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.300 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.100 mm table 118. ufbga176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. z & wz s ' s d g ' v p docid024244 rev 10 223/240 stm32f437xx and stm32f439xx package information 233 device marking for ufbga176+25 the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 100. ufbga176+25 marki ng example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 6 7 0 ) 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h \ h d u z h h n < : : % d o o l q g h q w l i l h u , , + 8 5 package information stm32f437xx and stm32f439xx 224/240 docid024244 rev 10 7.8 tfbga216 package information figure 101. tfbga216 - 216 ball 13 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline 1. drawing is not to scale. $ / b 0 ( b 9 6 h d w l q j s o d q h $ h ) * ' 5 ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : h $ $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d table 120. tfbga216 - 216 ball 13 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.100 - - 0.0433 a1 0.150 - - 0.0059 - - a2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 12.850 13.000 13.150 0.5118 0.5118 0.5177 d1 - 11.200 - - 0.4409 - e 12.850 13.000 13.150 0.5118 0.5118 0.5177 e1 - 11.200 - - 0.4409 - e - 0.800 - - 0.0315 - f - 0.900 - - 0.0354 - ddd - - 0.100 - - 0.0039 docid024244 rev 10 225/240 stm32f437xx and stm32f439xx package information 233 device marking for tfbga176 the following figure gives an example of topside marking orientation versus ball a1 identifier location. other optional marking or inset/upset marks, which depends assembly location, are not indicated below. figure 102. tfbga176 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 120. tfbga216 - 216 ball 13 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 0 6 y 9 % d o o $ l g h q w l i l h u ' d w h f r g h \ h d u z h h n < : : 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q 5 6 7 0 ) 1 , + package information stm32f437xx and stm32f439xx 226/240 docid024244 rev 10 7.9 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 121. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 43 c/w thermal resistance junction-ambient wlcsp143 31.2 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient lqfp208 - 28 28 mm / 0.5 mm pitch 19 thermal resistance junction-ambient ufbga169 - 7 7mm / 0.5 mm pitch 52 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.5 mm pitch 39 thermal resistance junction-ambient tfbga216 - 13 13 mm / 0.8 mm pitch 29 docid024244 rev 10 227/240 stm32f437xx and stm32f439xx part numbering 233 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 122. ordering information scheme example: stm32 f 439 v i t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 437= stm32f437xx, usb otg fs/hs, camera interface, ethernet, cryptographic acceleration 439= stm32f439xx, usb otg fs/hs, camera interface, ethernet, lcd-tft, cryptographic acceleration pin count v = 100 pins z = 143 and 144 pins a = 169 pins i = 176 pins b = 208 pins n = 216 pins flash memory size g = 1024 kbytes of flash memory i = 2048 kbytes of flash memory package t = lqfp h = bga y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel recommendations when using internal reset off stm32f437xx and stm32f439xx 228/240 docid024244 rev 10 appendix a recommendations wh en using internal reset off when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry must be disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and vbat pin should be connected to v dd . ? the over-drive mode is not supported. a.1 operating conditions table 123. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum flash memory access frequency with wait states (1)(2) 1. applicable only when the code is executed from flash memory. wh en the code is executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. i/o operation possible flash memory operations v dd =1.7 to 2.1 v (3) 3. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 3.17.1: internal reset on ). conversion time up to 1.2 msps 20 mhz (4) 4. prefetch is not available. refer to an3430 applicat ion note for details on how to adjust performance and power. 168 mhz with 8 wait states and over-drive off ? no i/o compensation 8-bit erase and program operations only docid024244 rev 10 229/240 stm32f437xx and stm32f439xx application block diagrams 233 appendix b application block diagrams b.1 usb otg full speed (fs) interface solutions figure 103. usb controller configured as peripheral-only and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. figure 104. usb controller configured as host-only and used in full speed mode 1. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. 3 4 - & x x 6 t o 6 $ $ 6 o l a t g e r e g u l a t o r 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 " 0 ! 0 " 5 3 " 3 t d " c o n n e c t o r $ - / 3 # ? ) . / 3 # ? / 5 4 - 3 6 3 4 - & x x 6 $ $ 6 " 5 3 $ 0 6 3 3 5 3 " 3 t d ! c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r / 3 # ? ) . / 3 # ? / 5 4 - 3 6 # u r r e n t l i m i t e r p o w e r s w i t c h 0 ! 0 " 0 ! 0 " application block diagrams stm32f437xx and stm32f439xx 230/240 docid024244 rev 10 figure 105. usb controller configured in dual mode and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3. the id pin is required in dual role only. 4. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. 3 4 - & x x 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 " 0 ! 0 " 0 ! 0 " 5 3 " m i c r o ! " c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r 6 t o 6 $ $ v o l t a g e r e g u l a t o r 6 $ $ ) $ 0 ! 0 " / 3 # ? ) . / 3 # ? / 5 4 - 3 6 # u r r e n t l i m i t e r p o w e r s w i t c h docid024244 rev 10 231/240 stm32f437xx and stm32f439xx application block diagrams 233 b.2 usb otg high speed (h s) interface solutions figure 106. usb controller configured as peripheral, host, or dual-mode and used in high speed mode 1. it is possible to use mco1 or mco2 to save a crys tal. it is however not mandatory to clock the stm32f43x with a 24 or 26 mhz crystal when using usb hs. the above figure only shows an example of a possible connection. 2. the id pin is required in dual role only. $ 0 3 4 - & x x $ - 6 " 5 3 6 3 3 $ - $ 0 ) $ 5 3 " 5 3 " ( 3 / 4 ' # t r l & 3 0 ( 9 5 , 0 ) ( i g h s p e e d / 4 ' 0 ( 9 5 , 0 ) ? # , + 5 , 0 ) ? $ ; = 5 , 0 ) ? $ ) 2 5 , 0 ) ? 3 4 0 5 , 0 ) ? . 8 4 n o t c o n n e c t e d c o n n e c t o r - # / o r - # / o r - ( z 8 4 0 , , 8 4 8 ) - 3 6 application block diagrams stm32f437xx and stm32f439xx 232/240 docid024244 rev 10 b.3 ethernet interface solutions figure 107. mii mode using a 25 mhz crystal 1. f hclk must be greater than 25 mhz. 2. pulse per second when using ieee1588 ptp optional signal. figure 108. rmii wi th a 50 mhz oscillator 1. f hclk must be greater than 25 mhz. - # 5 % t h e r n e t - ! # % t h e r n e t 0 ( 9 0 , , ( # , + 8 4 0 ( 9 ? # , + - ( z - ) ) ? 2 8 ? # , + - ) ) ? 2 8 $ ; = - ) ) ? 2 8 ? $ 6 - ) ) ? 2 8 ? % 2 - ) ) ? 4 8 ? # , + - ) ) ? 4 8 ? % . - ) ) ? 4 8 $ ; = - ) ) ? # 2 3 - ) ) ? # / , - $ ) / - $ # ( # , + 0 0 3 ? / 5 4 8 4 ! , - ( z 3 4 - / 3 # 4 ) - 4 i m e s t a m p c o m p a r a t o r 4 i m e r i n p u t t r i g g e r ) % % % 0 4 0 - ) ) p i n s - ) ) - $ # p i n s - 3 6 - # / - # / - # 5 % t h e r n e t - ! # % t h e r n e t 0 ( 9 0 , , ( # , + 8 4 0 ( 9 ? # , + - ( z 2 - ) ) ? 2 8 $ ; = 2 - ) ) ? # 2 8 ? $ 6 2 - ) ) ? 2 % & ? # , + 2 - ) ) ? 4 8 ? % . 2 - ) ) ? 4 8 $ ; = - $ ) / - $ # ( # , + 3 4 - / 3 # - ( z 4 ) - 4 i m e s t a m p c o m p a r a t o r 4 i m e r i n p u t t r i g g e r ) % % % 0 4 0 2 - ) ) p i n s 2 - ) ) - $ # p i n s - 3 6 o r s y n c h r o n o u s o r - ( z - ( z - ( z docid024244 rev 10 233/240 stm32f437xx and stm32f439xx application block diagrams 233 figure 109. rmii with a 25 mhz crystal and phy with pll 1. f hclk must be greater than 25 mhz. 2. the 25 mhz (phy_clk) must be derived directly from the hse oscillator, before the pll block. - # 5 % t h e r n e t - ! # % t h e r n e t 0 ( 9 0 , , ( # , + 8 4 0 ( 9 ? # , + - ( z 2 - ) ) ? 2 8 $ ; = 2 - ) ) ? # 2 8 ? $ 6 2 - ) ) ? 2 % & ? # , + 2 - ) ) ? 4 8 ? % . 2 - ) ) ? 4 8 $ ; = - $ ) / - $ # ( # , + 3 4 - & 4 ) - 4 i m e s t a m p c o m p a r a t o r 4 i m e r i n p u t t r i g g e r ) % % % 0 4 0 2 - ) ) p i n s 2 - ) ) - $ # p i n s - 3 6 o r s y n c h r o n o u s o r - ( z - ( z 8 4 ! , - ( z / 3 # 0 , , 2 % & ? # , + - # / - # / revision history stm32f437xx and stm32f439xx 234/240 docid024244 rev 10 9 revision history table 124. document revision history date revision changes 12-aug-2013 1 initial release. 10-sep-2013 2 added stm32f439xx part numbers and related informations. stm32f437xx part numbers: replaced fsmc by fmc added chrom-art accelerator and sai interface. increased core, timer, gpios, spi maximum frequencies updated figure 4: stm32f437xx and stm32f439xx block diagram . updated figure 5: stm32f437xx and stm32f439xx multi-ahb matrix . removed note in section : standby mode . updated figure 14: stm32f43x lqfp176 pinout . updated table 10: stm32f437xx and stm32f439xx pin and ball definitions and table 12: stm32f437xx and stm32f439xx alternate function mapping .. modified figure 19: memory map . updated table 17: general operating conditions , table 18: limitations depending on the operating power supply range . removed note 1 in table 22: reset and power control block characteristics . added table 23: over-drive switching characteristics . updated section : typical and maximum current consumption , table 34: switching output i/o current consumption , table 35: peripheral current consumption and section : on-chip peripheral current consumption . updated table 36: low-power mode wakeup timings . modified section : high-speed external user clock generated from an external source , section : low-speed external user clock generated from an external source , and section 6.3.10: inte rnal clock source characteristics . updated table 43: main pll characteristics and table 45: pllisai (audio and lcd-tft pll) characteristics . updated table 52: emi characteristics . updated table 57: output voltage characteristics and table 58: i/o ac characteristics . updated table 60: timx characteristics , table 61: i2c characteristics , table 62: spi dynamic characteristics , section : sai characteristics . updated table 102: sdram read timings and table 104: sdram write timings . docid024244 rev 10 235/240 stm32f437xx and stm32f439xx revision history 239 24-jan-2014 3 added stm32f437ai and stm32f439ai part numbers and ufbga169 package. changed intn into intr in figure 4: stm32f437xx and stm32f439xx block diagram . updated section 3.15: boot modes . updated for pa4 and pa5 in table 10: stm32f437xx and stm32f439xx pin and ball definitions . added v in for boot0 pins in table 14: voltage characteristics . updated note 6. added note 1. , and updated maximum v in for b pins in table 17: general operating conditions . updated maximum flash memory ac cess frequency with wait states for v dd =1.8 to 2.1 v in table 18: limitations depending on the operating power supply range . updated table 24: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram and table 25: typical and maximum current consumptio n in run mode, code with data processing running from flash memory (art accelerator disabled) . updated table 30: typical current consumption in run mode, code with data processing running from flash memory or ram, regulator on (art accelerator enabled except prefetch), vdd=1.7 v , table 31: typical current consumption in run mode, code with data processing running from flash memory, regu lator off (art a ccelerator enabled except prefetch) , and table 32: typical current consumption in sleep mode, regulator on, vdd=1.7 v . updated table 57: output voltage characteristics . updated table 58: i/o ac characteristics . added figure 35 . updated t h(sda) , t r(sda) and t r(scl) and added t sp in table 61: i2c characteristics . updated f sck in table 62: spi dynamic characteristics . updated table 70: dynamic characteristics: usb ulpi . updated section 6.3.26: fmc characteristics conditions. updated figure 73: sdram read access waveforms (cl = 1) and figure 74: sdram write access waveforms . added table 103: lpsdr sdram read timings and table 105: lpsdr sdram write timings . updated table 102: sdram read timings and table 104: sdram write timings and added note 2.table 108: dynamic characteristics: sd / mmc characteristics . 31-jan-2014 4 in the whole document, minimum supply voltage changed to 1.7 v when external power supply supervisor is used. updated conditions in table 62: spi dynamic characteristics . added z drv in table 67: usb otg full speed electrical characteristics table 124. document revision history (continued) date revision changes revision history stm32f437xx and stm32f439xx 236/240 docid024244 rev 10 24-apr-2014 5 changed svga (800x600) into xga1024x768) on cover page and in section 3.10: lcd-tft controller (available only on stm32f439xx) . added dcmi_vsync alternate function on pg9 and updated note 6. in table 10: stm32f437xx and stm32f439xx pin and ball definitions and table 12: stm32f437xx and stm32f439xx alternate function mapping . added note 2. below figure 16: stm32f43x ufbga169 ballout . updated section 3.18.2: regulator off . updated signal corresponding to pin l5 in figure 12: stm32f43x wlcsp143 ballout . updated table 53: esd absolute maximum ratings . updated v ih in table 56: i/o static characteristics . added condition v dd >1.7 v in table 58: i/o ac characteristics . removed notes 3 and 4 in table 62: spi dynamic characteristics . added acc hse in table 39: hse 4-26 mhz oscillator characteristics and acc lse in table 40: lse oscillator c haracteristics (flse = 32.768 khz) . removed note 3 in table 80: temperature sensor characteristics . added figure 82: lqfp100 marking example (package top view) , figure 85: wlcsp143 marking example (package top view) , figure 88: lqfp144 marking example (package top view) , figure 91: lqfp176 marking (package top view) , figure 94: lqfp208 marking example (package top view) , figure 97: ufbga169 marking example (package top view) and figure 100: ufbga176+25 marking example (package top view) . added appendix a: recommendations when using internal reset off and removed internal reset off hardware connection appendix. table 124. document revision history (continued) date revision changes docid024244 rev 10 237/240 stm32f437xx and stm32f439xx revision history 239 19-feb-2015 6 update spi/is2 in table 2: stm32f437xx and stm32f439xx features and peripheral counts . updated lqfp208 in table 4: regulator on/off and internal reset on/off availability . updated figure 19: memory map . changed pls[2:0]=101 (falling edge) maximum value in table 22: reset and power control block characteristics . updated current consumption with all peripherals disabled in table 24: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram . updated note 1. in table 28: typical and maximum current consumptions in standby mode . updated t wustop in table 36: low-power mode wakeup timings . updated esd standards and table 53: esd absolute maximum ratings . updated table 56: i/o static characteristics . section : i2c interface characteristics : updated section introduction, removed table i2c characteristics , figure i2c bus ac waveforms and measurement circuit and table scl frequency ; added table 61: i2c analog filter characteristics . updated measurement conditions in table 62: spi dynamic characteristics . updated figure 51: typical connection diagram using the adc . updated section : device marking for lqfp100 . updated figure 83: wlcsp143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline and table 111: wlcsp143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data ; added figure 84: wlcsp143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint and table 112: wlcsp143 recommended pcb design rules (0.4 mm pitch) . updated figure 85: wlcsp143 marking example (package top view) and related note. updated section : device marking for wlcsp143 . updated section : device marking for lqfp144 . updated section : device marking for lqfp176 . updated figure 92: lqfp208 - 208-pin, 28 x 28 mm low-profile quad flat package outline ; updated section : device marking for lqfp208 . modified ufbga169 pitch, updated figure 95: ufbga169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline and table 116: ufbga169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data ; updated section : device marking for lqfp208 . updated section : device marking for ufbga169 , section : device marking for ufbga176+25 and section : device marking for tfbga176 . updated z pin count in table 122: ordering information scheme . table 124. document revision history (continued) date revision changes revision history stm32f437xx and stm32f439xx 238/240 docid024244 rev 10 28-sep-2015 7 updated notes related to the minimum and maximum values guaranteed by design, characterization or test in production. updated i dd_stop_udm in table 27: typical and maximum current consumptions in stop mode . removed note related to tests in production in table 24: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabled except prefetch) or ram and table 26: typical and maximum current consumption in sleep mode . updated table 41: hsi oscillator characteristics . figure 31 renamed acchsi accuracy versus temperature and updated. updated figure 38: spi timing diagram - slave mode and cpha = 0 . updated section : ethernet characteristics . updated table 43: main pll characteristics , table 44: plli2s (audio pll) characteristics and table 45: pllisai (audio and lcd-tft pll) characteristics . removed note 1 in table 75: adc static accuracy at fadc = 18 mhz , table 76: adc static accuracy at fadc = 30 mhz and table 77: adc static accuracy at fadc = 36 mhz . updated t d(sdclkl _data ) and t h(sdclkl _data) in table 104: sdram write timings . updated note below marking schematics. added figure 96: ufbga169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint and table 117: ufbga169 recommended pcb design rules (0.5 mm pitch bga) . added figure 99: ufbga176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint and table 119: ufbga176+25 recommended pcb design rules (0.65 mm pitch bga) . 30-nov-2015 8 updated |v ssx ? v ss | in table 14: voltage characteristics to add v ref- . updated t d(txen) and t d(txd) minimum value in table 72: dynamics characteristics: ethernet mac signals for rmii and table 73: dynamics characteristics: ether net mac signals for mii . added v ref- in table 74: adc characteristics . added a1 minimum and maximum values in table 111: wlcsp143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data . updated figure 86: lqfp144-144-pin, 20 x 20 mm low-profile quad flat package outline .updated figure 98: ufbga176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline and table 118: ufbga176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . updated figure 101: tfbga216 - 216 ball 13 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline and table 120: tfbga216 - 216 ball 13 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data . table 124. document revision history (continued) date revision changes docid024244 rev 10 239/240 stm32f437xx and stm32f439xx revision history 239 11-jan-2016 9 updated figure 22: power supply scheme . added t d(txd) values corresponding to 1.71 v < v dd < 3.6 v in table 72: dynamics characteristi cs: ethernet mac signals for rmii . 18-jul-2016 10 updated figure 1: compatible board design stm32f10xx/stm32f2xx/stm32f4xx for lqfp100 package . added mission profile comp liance with jedec jesd47 in section 6.2: absolute maximum ratings . changed figure 31 hsi deviation versus temperature to acchsi versus temperature. updated r load in table 85: dac characteristics . added note 2. related to the position of the external capacitor below figure 37: recommended nrst pin protection . updated figure 40: spi timing diagram - master mode . added reference to optional marking or inset/upset marks in all package device marking sections. updated figure 85: wlcsp143 marking example (package top view) , figure 88: lqfp144 marking example (package top view) , figure 91: lqfp176 marking (package top view) , figure 94: lqfp208 marking example (package top view) , figure 97: ufbga169 marking example (package top view) , figure 102: tfbga176 marking example (package top view) . updated figure 98: ufbga176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline and table 118: ufbga176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . table 124. document revision history (continued) date revision changes stm32f437xx and stm32f439xx 240/240 docid024244 rev 10 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
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